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Initial checkin of new WIP Z80 core using CPU DSL
author Michael Pavone <pavone@retrodev.com>
date Mon, 28 Jan 2019 21:16:41 -0800
parents
children 0a9a88b3d061
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rev   line source
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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1 info
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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2 prefix z80_
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3 opcode_size 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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4 extra_tables cb ed dded fded dd fd
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5 body z80_run_op
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6 include z80_util.c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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7 header z80.h
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8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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9 regs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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10 main 8 b c d e h l f a
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11 alt 8 b' c' d' e' h' l' f' a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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12 i 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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13 r 8
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14 iff1 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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15 iff2 8
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16 imode 8
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17 sp 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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18 ix 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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19 iy 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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20 pc 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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21 wz 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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22 nflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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23 last_flag_result 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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24 pvflag 8
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25 chflags 8
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26 zflag 8
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27 scratch1 16
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28 scratch2 16
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29
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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30 flags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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31 register f
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32 S 7 sign last_flag_result.7
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33 Z 6 zero zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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34 Y 5 bit-5 last_flag_result.5
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35 H 4 half-carry chflags.3
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36 P 2 parity pvflag
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37 V 2 overflow pvflag
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38 X 3 bit-3 last_flag_result.3
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39 N 1 none nflag
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40 C 0 carry chflags.7
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41
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42
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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43 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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44 cycles 1
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45 add 1 r r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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46 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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47 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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48 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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49
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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50 z80_run_op
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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51 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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52 dispatch scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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53
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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54 11001011 cb_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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55 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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56 dispatch scratch1 cb
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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57
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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58 11011101 dd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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59 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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60 dispatch scratch1 dd
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61
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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62 11011101 ed_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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63 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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64 dispatch scratch1 ed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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65
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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66 11111101 fd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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67 z80_op_fetch
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68 dispatch scratch1 fd
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69
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70 z80_check_cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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71 arg cond 8
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72 local invert 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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73 switch cond
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74 case 0
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75 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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76 lnot zflag invert
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77
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78 case 1
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79 meta istrue zflag
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80
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81 case 2
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82 meta istrue invert
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83 not chflags invert
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84 and 0x80 invert invert
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85
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86 case 3
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87 meta istrue invert
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88 and 0x80 invert invert
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89
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90 case 4
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91 meta istrue invert
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92 lnot pvflag invert
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93
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94 case 5
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95 meta istrue pvflag
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96
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97 case 6
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98 meta istrue invert
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99 not last_flag_result invert
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100 and 0x80 invert invert
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101
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102 case 7
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103 meta istrue invert
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104 and 0x80 last_flag_result invert
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105
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106 end
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107
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108 z80_fetch_hl
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109 lsl h 8 scratch1
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110 or l scratch1 scratch1
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111 ocall read_8
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112
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113 z80_store_hl
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114 lsl h 8 scratch2
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115 or l scratch2 scratch2
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116 ocall write_8
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117
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118 z80_fetch_immed
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119 mov pc scratch1
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120 ocall read_8
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121 add 1 pc pc
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122
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123 z80_fetch_immed16
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124 mov pc scratch1
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125 ocall read_8
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126 mov scratch1 wz
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127 add 1 pc pc
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128 mov pc scratch1
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129 ocall read_8
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130 add 1 pc pc
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131 lsl scratch1 8 scratch1
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132 or scratch1 wz wz
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133
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134 z80_fetch_immed_reg16
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135 mov pc scratch1
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136 ocall read_8
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137 mov scratch1 low
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138 add 1 pc pc
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139 mov pc scratch1
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140 ocall read_8
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141 mov scratch1 high
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142 add 1 pc pc
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143
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144 z80_fetch_immed_to_reg16
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145 mov pc scratch1
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parents:
diff changeset
146 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 z80_calc_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157 add scratch1 index wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 z80_fetch_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 z80_calc_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 z80_fetch_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 meta index ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 z80_fetch_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 z80_fetch_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 meta index iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 z80_fetch_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 01DDDSSS ld_from_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 mov main.S main.D
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 dd 01RRR110 ld_from_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181 z80_fetch_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
184 fd 01RRR110 ld_from_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185 z80_fetch_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 01110RRR ld_to_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 dd 01110RRR ld_to_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 meta index ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 z80_calc_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 fd 01110RRR ld_to_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204 meta index iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 z80_calc_index
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 00001010 ld_a_from_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 or c scratch2 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 00011010 ld_a_from_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 lsl d 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 or e scratch2 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 00000010 ld_a_to_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 00010010 ld_a_to_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 lsl d 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 or e scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 00110010 ld_a_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 ed 01000111 ld_i_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 mov a i
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 ed 01001111 ld_r_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 mov a r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 meta high c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 mov l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 mov h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 local sph 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 lsr sp 8 sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 lsl h 8 sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 or l sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 lsr sp 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 local ixh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 lsr ix 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 local iyh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 lsr iy 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 lsl ixh 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 or ixh ix ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 lsl iyh 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 or iyh iy iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 11100011 ex_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 add 1 sp wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 10000RRR add_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 add a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 or a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
590 or a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
591 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
592
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
593 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 or a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 xor a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 xor a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 xor a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 10111RRR cp_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 cmp main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 10111110 cp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 cmp scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 11111110 cp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 cmp scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 00110100 inc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 #TODO: fix size
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 add 1 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 00RRR101 dec_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 00110101 dec_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 #TODO: fix size
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 add 1 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 00101111 cpl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 not a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 11101101 neg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 neg a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 00111111 ccf
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 xor 0x80 chflags chflags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 00111111 scf
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 or 0x80 chflags chflags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 11110011 di
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 mov 0 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 mov 0 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 11111011 ei
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 mov 1 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 mov 1 iff2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 #TODO: update interrupt/sync cycle
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 ed 01000110 im0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 ed 01010110 im1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 ed 01011110 im2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
698 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
699 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
700 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
701 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
702
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
703 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
704 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
705 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
707 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
708
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
709 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
710 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
711 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
712
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
713 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
714
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
715 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
716 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
717 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
718 sub 1 b b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
719
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
720 if b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
721
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
722 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
723 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
724 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
725
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
726 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
727
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
730 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
735 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
736 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
737
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
738 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
739 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
740 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
741 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
742 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
743 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
744 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
745 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
746
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
747 11001001 ret
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
748 #TODO: confirm this goes through wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
749 local wzh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
750 meta high wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
751 meta low wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
752 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753 lsl wzh 8 wzh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754 or wzh wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
755 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
758 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
759 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
760 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
761
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
762 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
763 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
764 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
765 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
766 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
767
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
768 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
769 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
770 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
771 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
772 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
773
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
774 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
775 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
776 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
777 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
778 ocall io_write8