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annotate cpu_dsl.py @ 1614:c9639139aedf

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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
author Michael Pavone <pavone@retrodev.com>
date Fri, 21 Sep 2018 09:26:12 -0700
parents 2d9e8a7b8ba2
children 28f80d1b343e
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1613
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1 #!/usr/bin/env python3
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2
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3
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4 class Block:
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5 def addOp(self, op):
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6 pass
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7
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8 def processLine(self, parts):
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9 if parts[0] == 'switch':
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10 o = Switch(self, parts[1])
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11 self.addOp(o)
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12 return o
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13 elif parts[0] == 'if':
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14 o = If(self, parts[1])
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15 self.addOp(o)
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16 return o
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17 elif parts[0] == 'end':
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18 raise Exception('end is only allowed inside a switch or if block')
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19 else:
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20 self.addOp(NormalOp(parts))
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21 return self
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22
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23 def resolveLocal(self, name):
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24 return None
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25
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26 class ChildBlock(Block):
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27 def processLine(self, parts):
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28 if parts[0] == 'end':
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29 return self.parent
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30 return super().processLine(parts)
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31
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32 #Represents an instruction of the emulated CPU
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33 class Instruction(Block):
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34 def __init__(self, value, fields, name):
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35 self.value = value
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36 self.fields = fields
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37 self.name = name
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38 self.implementation = []
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39 self.locals = {}
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40 self.regValues = {}
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41 self.varyingBits = 0
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42 self.invalidFieldValues = {}
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43 for field in fields:
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44 self.varyingBits += fields[field][1]
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45
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46 def addOp(self, op):
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47 if op.op == 'local':
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48 name = op.params[0]
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49 size = op.params[1]
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50 self.locals[name] = size
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51 elif op.op == 'invalid':
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52 name = op.params[0]
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53 value = int(op.params[1])
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54 self.invalidFieldValues.setdefault(name, set()).add(value)
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55 else:
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56 self.implementation.append(op)
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57
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58 def resolveLocal(self, name):
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59 if name in self.locals:
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60 return name
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61 return None
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62
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63 def addLocal(self, name, size):
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64 self.locals[name] = size
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65
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66 def localSize(self, name):
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67 return self.locals.get(name)
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68
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69 def __lt__(self, other):
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70 if isinstance(other, Instruction):
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71 if self.varyingBits != other.varyingBits:
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72 return self.varyingBits < other.varyingBits
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73 return self.value < other.value
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74 else:
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75 return NotImplemented
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76
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77 def allValues(self):
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78 values = []
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79 for i in range(0, 1 << self.varyingBits):
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80 iword = self.value
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81 doIt = True
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82 for field in self.fields:
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83 shift,bits = self.fields[field]
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84 val = i & ((1 << bits) - 1)
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85 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]:
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86 doIt = False
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87 break
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88 i >>= bits
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89 iword |= val << shift
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90 if doIt:
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91 values.append(iword)
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92 return values
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93
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94 def getFieldVals(self, value):
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95 fieldVals = {}
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96 fieldBits = {}
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97 for field in self.fields:
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98 shift,bits = self.fields[field]
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99 val = (value >> shift) & ((1 << bits) - 1)
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100 fieldVals[field] = val
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101 fieldBits[field] = bits
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102 return (fieldVals, fieldBits)
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103
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104 def generateName(self, value):
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105 fieldVals,fieldBits = self.getFieldVals(value)
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106 names = list(fieldVals.keys())
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107 names.sort()
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108 funName = self.name
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109 for name in names:
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110 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name])
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111 return funName
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112
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113 def generateBody(self, value, prog, otype):
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114 output = []
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115 prog.meta = {}
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116 prog.currentScope = self
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117 self.regValues = {}
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118 for var in self.locals:
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119 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var))
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120 fieldVals,_ = self.getFieldVals(value)
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121 for op in self.implementation:
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122 op.generate(prog, self, fieldVals, output, otype)
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123 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{'
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124 if prog.needFlagCoalesce:
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125 begin += prog.flags.coalesceFlags(prog, otype)
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126 if prog.needFlagDisperse:
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127 output.append(prog.flags.disperseFlags(prog, otype))
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128 return begin + ''.join(output) + '\n}'
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129
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130 def __str__(self):
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131 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)]
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132 for name in self.locals:
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133 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
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134 for op in self.implementation:
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135 pieces.append(str(op))
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136 return ''.join(pieces)
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137
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138 #Represents the definition of a helper function
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139 class SubRoutine(Block):
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140 def __init__(self, name):
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141 self.name = name
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142 self.implementation = []
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143 self.args = []
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144 self.arg_map = {}
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145 self.locals = {}
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146 self.regValues = {}
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147
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148 def addOp(self, op):
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149 if op.op == 'arg':
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150 name = op.params[0]
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151 size = op.params[1]
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152 self.arg_map[name] = len(self.args)
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153 self.args.append((name, size))
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154 elif op.op == 'local':
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155 name = op.params[0]
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156 size = op.params[1]
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157 self.locals[name] = size
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158 else:
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159 self.implementation.append(op)
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160
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161 def resolveLocal(self, name):
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162 if name in self.locals:
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163 return self.name + '_' + name
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164 return None
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165
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166 def addLocal(self, name, size):
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167 self.locals[name] = size
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168
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169 def localSize(self, name):
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170 return self.locals.get(name)
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171
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172 def inline(self, prog, params, output, otype, parent):
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173 if len(params) != len(self.args):
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174 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params)))
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175 argValues = {}
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176 if parent:
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177 self.regValues = parent.regValues
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178 oldScope = prog.currentScope
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179 prog.currentScope = self
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180 i = 0
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181 for name,size in self.args:
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182 argValues[name] = params[i]
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183 i += 1
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184 for name in self.locals:
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185 size = self.locals[name]
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186 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name))
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187 for op in self.implementation:
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188 op.generate(prog, self, argValues, output, otype)
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189 prog.currentScope = oldScope
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190
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191 def __str__(self):
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192 pieces = [self.name]
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193 for name,size in self.args:
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194 pieces.append('\n\targ {0} {1}'.format(name, size))
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195 for name in self.locals:
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196 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
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197 for op in self.implementation:
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198 pieces.append(str(op))
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199 return ''.join(pieces)
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200
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201 class Op:
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202 def __init__(self, evalFun = None):
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203 self.evalFun = evalFun
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204 self.impls = {}
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205 self.outOp = ()
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206 def cBinaryOperator(self, op):
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207 def _impl(prog, params):
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208 if op == '-':
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209 a = params[1]
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210 b = params[0]
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211 else:
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212 a = params[0]
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213 b = params[1]
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214 return '\n\t{dst} = {a} {op} {b};'.format(
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215 dst = params[2], a = a, b = b, op = op
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216 )
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217 self.impls['c'] = _impl
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218 self.outOp = (2,)
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219 return self
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220 def cUnaryOperator(self, op):
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221 def _impl(prog, params):
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222 return '\n\t{dst} = {op}{a};'.format(
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223 dst = params[1], a = params[0], op = op
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224 )
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225 self.impls['c'] = _impl
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226 self.outOp = (1,)
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227 return self
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228 def addImplementation(self, lang, outOp, impl):
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229 self.impls[lang] = impl
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230 if not outOp is None:
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231 if type(outOp) is tuple:
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232 self.outOp = outOp
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233 else:
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234 self.outOp = (outOp,)
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235 return self
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236 def evaluate(self, params):
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237 return self.evalFun(*params)
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238 def canEval(self):
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239 return not self.evalFun is None
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240 def numArgs(self):
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241 return self.evalFun.__code__.co_argcount
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242 def generate(self, otype, prog, params, rawParams):
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243 if self.impls[otype].__code__.co_argcount == 2:
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244 return self.impls[otype](prog, params)
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245 else:
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246 return self.impls[otype](prog, params, rawParams)
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247
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248
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249 def _xchgCImpl(prog, params, rawParams):
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250 size = prog.paramSize(rawParams[0])
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251 decl,name = prog.getTemp(size)
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252 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name)
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253
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254 def _dispatchCImpl(prog, params):
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255 if len(params) == 1:
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256 table = 'main'
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257 else:
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258 table = params[1]
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259 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0])
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260
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261 def _updateFlagsCImpl(prog, params, rawParams):
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262 i = 0
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263 last = ''
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264 autoUpdate = set()
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265 explicit = {}
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266 for c in params[0]:
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267 if c.isdigit():
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268 if last.isalpha():
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269 num = int(c)
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270 if num > 1:
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271 raise Exception(c + ' is not a valid digit for update_flags')
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272 explicit[last] = num
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273 last = c
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274 else:
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275 raise Exception('Digit must follow flag letter in update_flags')
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276 else:
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277 if last.isalpha():
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278 autoUpdate.add(last)
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279 last = c
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280 if last.isalpha():
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281 autoUpdate.add(last)
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282 output = []
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283 #TODO: handle autoUpdate flags
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284 for flag in autoUpdate:
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285 calc = prog.flags.flagCalc[flag]
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286 calc,_,resultBit = calc.partition('-')
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287 lastDst = prog.resolveReg(prog.lastDst, None, {})
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288 storage = prog.flags.getStorage(flag)
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289 if calc == 'bit' or calc == 'sign':
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290 if calc == 'sign':
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291 resultBit = prog.paramSize(prog.lastDst) - 1
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292 else:
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293 resultBit = int(resultBit)
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294 if type(storage) is tuple:
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295 reg,storageBit = storage
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296 reg = prog.resolveReg(reg, None, {})
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297 if storageBit == resultBit:
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diff changeset
298 #TODO: optimize this case
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diff changeset
299 output.append('\n\t{reg} = ({reg} & ~{mask}) | ({res} & {mask});'.format(
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300 reg = reg, mask = 1 << resultBit, res = lastDst
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301 ))
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302 else:
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303 if resultBit > storageBit:
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304 op = '>>'
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305 shift = resultBit - storageBit
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306 else:
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307 op = '<<'
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308 shift = storageBit - resultBit
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309 output.append('\n\t{reg} = ({reg} & ~{mask}) | ({res} {op} {shift} & {mask});'.format(
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310 reg = reg, mask = 1 << storageBit, res = lastDst, op = op, shift = shift
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diff changeset
311 ))
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diff changeset
312 else:
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313 reg = prog.resolveReg(storage, None, {})
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314 output.append('\n\t{reg} = {res} & {mask};'.format(reg=reg, res=lastDst, mask = 1 << resultBit))
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315 elif calc == 'zero':
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316 if type(storage) is tuple:
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317 reg,storageBit = storage
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318 reg = prog.resolveReg(reg, None, {})
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319 output.append('\n\t{reg} = {res} ? ({reg} & {mask}) : ({reg} | {bit});'.format(
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diff changeset
320 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
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321 ))
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322 elif prog.paramSize(prog.lastDst) > prog.paramSize(storage):
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323 reg = prog.resolveReg(storage, None, {})
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324 output.append('\n\t{reg} = {res} != 0;'.format(
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diff changeset
325 reg = reg, res = lastDst
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diff changeset
326 ))
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diff changeset
327 else:
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328 reg = prog.resolveReg(storage, None, {})
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diff changeset
329 output.append('\n\t{reg} = {res};'.format(reg = reg, res = lastDst))
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diff changeset
330 elif calc == 'half-carry':
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diff changeset
331 pass
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diff changeset
332 elif calc == 'carry':
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diff changeset
333 pass
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diff changeset
334 elif calc == 'overflow':
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diff changeset
335 pass
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diff changeset
336 elif calc == 'parity':
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diff changeset
337 pass
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diff changeset
338 #TODO: combine explicit flags targeting the same storage location
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diff changeset
339 for flag in explicit:
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diff changeset
340 location = prog.flags.getStorage(flag)
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diff changeset
341 if type(location) is tuple:
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diff changeset
342 reg,bit = location
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diff changeset
343 reg = prog.resolveReg(reg, None, {})
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344 value = str(1 << bit)
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diff changeset
345 if explicit[flag]:
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diff changeset
346 operator = '|='
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diff changeset
347 else:
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diff changeset
348 operator = '&='
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diff changeset
349 value = '~' + value
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diff changeset
350 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value))
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diff changeset
351 else:
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diff changeset
352 reg = prog.resolveReg(location, None, {})
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diff changeset
353 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag]))
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diff changeset
354 return ''.join(output)
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diff changeset
355
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diff changeset
356 def _cmpCImpl(prog, params):
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357 size = prog.paramSize(params[1])
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diff changeset
358 tmpvar = 'cmp_tmp{sz}__'.format(sz=size)
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diff changeset
359 typename = ''
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360 if not prog.currentScope.resolveLocal(tmpvar):
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361 prog.currentScope.addLocal(tmpvar, size)
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362 typename = 'uint{sz}_t '.format(sz=size)
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diff changeset
363 prog.lastDst = tmpvar
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diff changeset
364 return '\n\t{tp}{var} = {b} - {a};'.format(tp = typename, var = tmpvar, a = params[0], b = params[1])
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parents:
diff changeset
365
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366 def _asrCImpl(prog, params, rawParams):
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367 shiftSize = prog.paramSize(rawParams[0])
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368 mask = 1 << (shiftSize - 1)
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diff changeset
369 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask}'.format(a = params[0], b = params[1], dst = params[2], mask = mask)
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diff changeset
370
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371 _opMap = {
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372 'mov': Op(lambda val: val).cUnaryOperator(''),
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373 'not': Op(lambda val: ~val).cUnaryOperator('~'),
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374 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
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375 'neg': Op(lambda val: -val).cUnaryOperator('-'),
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376 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
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377 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
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378 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
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379 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
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380 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
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381 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),
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382 'or': Op(lambda a, b: a | b).cBinaryOperator('|'),
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383 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
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384 'cmp': Op().addImplementation('c', None, _cmpCImpl),
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385 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
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386 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
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387 )),
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388 'cycles': Op().addImplementation('c', None,
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389 lambda prog, params: '\n\tcontext->current_cycle += context->opts->gen.clock_divider * {0};'.format(
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390 params[0]
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391 )
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392 ),
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393 'addsize': Op(
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394 lambda a, b: b + (2 * a if a else 1)
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395 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format(
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396 dst = params[1], sz = params[0], val = params[1]
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397 )),
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398 'decsize': Op(
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399 lambda a, b: b - (2 * a if a else 1)
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400 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format(
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401 dst = params[2], sz = params[0], val = params[1]
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402 )),
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403 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl),
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404 'dispatch': Op().addImplementation('c', None, _dispatchCImpl),
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405 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl)
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406 }
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407
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408 #represents a simple DSL instruction
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409 class NormalOp:
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410 def __init__(self, parts):
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411 self.op = parts[0]
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412 self.params = parts[1:]
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413
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414 def generate(self, prog, parent, fieldVals, output, otype):
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415 procParams = []
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416 allParamsConst = True
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417 opDef = _opMap.get(self.op)
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418 for param in self.params:
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419 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues
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420 isDst = (not opDef is None) and len(procParams) in opDef.outOp
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421 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst)
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422
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423 if (not type(param) is int) and len(procParams) != len(self.params) - 1:
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424 allParamsConst = False
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425 procParams.append(param)
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426
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427 if self.op == 'meta':
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428 param,_,index = self.params[1].partition('.')
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429 if index:
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430 index = (parent.resolveLocal(index) or index)
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431 if index in fieldVals:
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432 index = str(fieldVals[index])
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433 param = param + '.' + index
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434 else:
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435 param = parent.resolveLocal(param) or param
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436 if param in fieldVals:
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437 param = fieldVals[index]
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438 prog.meta[self.params[0]] = param
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439 elif self.op == 'dis':
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440 #TODO: Disassembler
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441 pass
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442 elif not opDef is None:
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443 if opDef.canEval() and allParamsConst:
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444 #do constant folding
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445 if opDef.numArgs() >= len(procParams):
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446 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')')
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447 dst = self.params[opDef.numArgs()]
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448 result = opDef.evaluate(procParams[:opDef.numArgs()])
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449 while dst in prog.meta:
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450 dst = prog.meta[dst]
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451 maybeLocal = parent.resolveLocal(dst)
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452 if maybeLocal:
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453 dst = maybeLocal
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454 parent.regValues[dst] = result
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455 if prog.isReg(dst):
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456 output.append(_opMap['mov'].generate(otype, prog, procParams, self.params))
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457 else:
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458 output.append(opDef.generate(otype, prog, procParams, self.params))
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459 elif self.op in prog.subroutines:
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460 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent)
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461 else:
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462 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');')
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463 prog.lastOp = self
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464
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465 def __str__(self):
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466 return '\n\t' + self.op + ' ' + ' '.join(self.params)
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467
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468 #represents a DSL switch construct
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469 class Switch(ChildBlock):
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470 def __init__(self, parent, param):
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471 self.op = 'switch'
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472 self.parent = parent
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473 self.param = param
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474 self.cases = {}
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475 self.regValues = None
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476 self.current_locals = {}
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477 self.case_locals = {}
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478 self.current_case = None
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479 self.default = None
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480 self.default_locals = None
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481
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482 def addOp(self, op):
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483 if op.op == 'case':
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484 self.cases[int(op.params[0])] = self.current_case = []
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485 self.case_locals[int(op.params[0])] = self.current_locals = {}
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486 elif op.op == 'default':
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487 self.default = self.current_case = []
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488 self.default_locals = self.current_locals = {}
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 elif self.current_case == None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 raise ion('Orphan instruction in switch')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 self.current_case.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 return self.parent.resolveLocal(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 return self.current_locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 return self.parent.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 def generate(self, prog, parent, fieldVals, output, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 oldScope = prog.currentScope
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 prog.currentScope = self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 param = prog.resolveParam(self.param, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 if type(param) is int:
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
516 self.regValues = self.parent.regValues
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 if param in self.cases:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 if self.case_locals[param]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 for local in self.case_locals[param]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 for op in self.cases[param]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 if self.case_locals[param]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 elif self.default:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 if self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 for local in self.default:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 for op in self.default:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 output.append('\n\tswitch(' + param + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 for case in self.cases:
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
537 self.regValues = dict(self.parent.regValues)
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 output.append('\n\tcase {0}: '.format(case) + '{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 for local in self.case_locals[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 for op in self.cases[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 output.append('\n\tbreak;')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 if self.default:
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
546 self.regValues = dict(self.parent.regValues)
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 output.append('\n\tdefault: {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 for local in self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 for op in self.default:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 prog.currentScope = oldScope
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 keys = self.cases.keys()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 keys.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 lines = ['\n\tswitch']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 for case in keys:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 lines.append('\n\tcase {0}'.format(case))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 lines.append(''.join([str(op) for op in self.cases[case]]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 def _geuCImpl(prog, parent, fieldVals, output):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 if prog.lastOp.op == 'cmp':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 output.pop()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 params = prog.lastOp.params
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 for i in range(0, len(params)):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 params[i] = prog.resolveParam(params[i], parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 return '\n\tif ({a} >= {b}) '.format(a=params[0], b = params[1]) + '{'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 raise ion(">=U not implemented in the general case yet")
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 _ifCmpImpl = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 'c': {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 '>=U': _geuCImpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 #represents a DSL conditional construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 class If(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583 def __init__(self, parent, cond):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 self.op = 'if'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 self.cond = cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587 self.body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 self.elseBody = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 self.curBody = self.body
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
590 self.locals = {}
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
591 self.elseLocals = {}
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
592 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
593 self.regValues = None
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596 if op.op in ('case', 'arg'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597 raise Exception(self.op + ' is not allows inside an if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 elif op.op == 'else':
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
603 self.curLocals = self.elseLocals
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 self.curBody = self.elseBody
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 self.curBody.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
608 def localSize(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
609 return self.curLocals.get(name)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
610
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
611 def resolveLocal(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
612 if name in self.locals:
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
613 return name
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
614 return None
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
615
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
616 def _genTrueBody(self):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
617 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
618 for op in self.body:
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
619 op.generate(prog, self, fieldVals, output, otype)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
620
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
621 def _genFalseBody(self):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
622 self.curLocals = self.elseLocals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
623 for op in self.body:
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
624 op.generate(prog, self, fieldVals, output, otype)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
625
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
626 def _genConstParam(self, param):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
627 if param:
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
628 self._genTrueBody()
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
629 else:
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
630 self._genFalseBody()
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
631
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 def generate(self, prog, parent, fieldVals, output, otype):
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
633 self.regValues = parent.regValues
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 try:
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
635 self._genConstParam(prog.checkBool(self.cond))
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 except Exception:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 if self.cond in _ifCmpImpl[otype]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 if self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 output.append('\n\t} else {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 for op in self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 cond = prog.resolveParam(self.cond, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 if type(cond) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 if cond:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 for op in self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 else:
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
656 output.append('\n\tif ({cond}) '.format(cond=cond) + '{')
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 if self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 output.append('\n\t} else {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 for op in self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 op.generate(prog, self, fieldVals, output, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 lines = ['\n\tif']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 lines.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 class Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 self.regs = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 self.regArrays = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 self.regToArray = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 def addReg(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 self.regs[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 def addRegArray(self, name, size, regs):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 self.regArrays[name] = (size, regs)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 idx = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 for reg in regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 self.regs[reg] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 self.regToArray[reg] = (name, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 idx += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691 return name in self.regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 def isRegArray(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 return name in self.regArrays
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 def isRegArrayMember(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697 return name in self.regToArray
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
698
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
699 def arrayMemberParent(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
700 return self.regToArray[name][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
701
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
702 def arrayMemberIndex(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
703 return self.regToArray[name][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
704
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
705 def arrayMemberName(self, array, index):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
706 if type(index) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
707 return self.regArrays[array][1][index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
708 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
709 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
710
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
711 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
712 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
713 self.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
714 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
715 self.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
716 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
717
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
718 class Flags:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
719 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
720 self.flagBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
721 self.flagCalc = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
722 self.flagStorage = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
723 self.flagReg = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
724 self.maxBit = -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
725
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
726 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
727 if parts[0] == 'register':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728 self.flagReg = parts[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
730 flag,bit,calc,storage = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731 bit,_,top = bit.partition('-')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732 bit = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733 if top:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 top = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
735 if top > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
736 self.maxBit = top
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
737 self.flagBits[flag] = (bit,top)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
738 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
739 if bit > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
740 self.maxBit = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
741 self.flagBits[flag] = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
742 self.flagCalc[flag] = calc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
743 self.flagStorage[flag] = storage
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
744 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
745
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
746 def getStorage(self, flag):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
747 if not flag in self.flagStorage:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
748 raise Exception('Undefined flag ' + flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
749 loc,_,bit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
750 if bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
751 return (loc, int(bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
752 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753 return loc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
755 def disperseFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757 src = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
758 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
759 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
760 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
761 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
762 bot,top = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
763 mask = ((1 << (top + 1 - bot)) - 1) << bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
764 output.append('\n\t{dst} = {src} & mask;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
765 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
766 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
767 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
768 bitToFlag[self.flagBits[flag]] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
769 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
770 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
771 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
772 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
773 field,_,dstbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
774 dst = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
775 if dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
776 dstbit = int(dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
777 multi.setdefault(dst, []).append((dstbit, bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
778 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
779 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
780 for dst in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
781 didClear = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
782 direct = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
783 for dstbit, bit in multi[dst]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
784 if dstbit == bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
785 direct.append(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
786 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
787 if not didClear:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
788 output.append('\n\t{dst} = 0;'.format(dst=dst))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
789 didClear = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
790 if dstbit > bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
791 shift = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
792 diff = dstbit - bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
793 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
794 shift = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
795 diff = bit - dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
796 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
797 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
798 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
799 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
800 if len(direct) == len(multi[dst]):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
801 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
802 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
803 mask = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
804 for bit in direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
805 mask = mask | (1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
806 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
807 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
808
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
809 def coalesceFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
810 dst = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
811 output = ['\n\t{dst} = 0;'.format(dst=dst)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
812 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
813 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
814 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
815 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
816 bot,_ = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
817 src = prog.resolveReg(self.flagStorage[flag], None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
818 if bot:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
819 output.append('\n\t{dst} |= {src} << {shift};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
820 dst=dst, src = src, shift = bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
821 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
822 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
823 output.append('\n\t{dst} |= {src};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
824 dst=dst, src = src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
825 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
826 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
827 bitToFlag[bit] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
828 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
829 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
830 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
831 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
832 field,_,srcbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
833 src = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
834 if srcbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
835 srcbit = int(srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
836 multi.setdefault(src, []).append((srcbit,bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
837 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
838 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
839 dst=dst, src=src, bit=bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
840 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
841 for src in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
842 direct = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
843 for srcbit, dstbit in multi[src]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
844 if srcbit == dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
845 direct = direct | (1 << srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
846 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
847 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
848 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
849 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
850 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
851 output.append('\n\t{dst} |= {src} & {mask}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
852 dst=dst, src=src, mask=direct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
853 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
854 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
855
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
856
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
857 class Program:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
858 def __init__(self, regs, instructions, subs, info, flags):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
859 self.regs = regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
860 self.instructions = instructions
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
861 self.subroutines = subs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
862 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
863 self.booleans = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
864 self.prefix = info.get('prefix', [''])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
865 self.opsize = int(info.get('opcode_size', ['8'])[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
866 self.extra_tables = info.get('extra_tables', [])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
867 self.context_type = self.prefix + 'context'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
868 self.body = info.get('body', [None])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
869 self.flags = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
870 self.lastDst = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
871 self.currentScope = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
872 self.lastOp = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
873
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
874 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
875 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
876 for reg in self.regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
877 pieces.append(str(self.regs[reg]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
878 for name in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
879 pieces.append('\n'+str(self.subroutines[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
880 for instruction in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
881 pieces.append('\n'+str(instruction))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
882 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
883
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
884 def build(self, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
885 body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
886 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
887 for table in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
888 opmap = [None] * (1 << self.opsize)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
889 bodymap = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
890 instructions = self.instructions[table]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
891 instructions.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
892 for inst in instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
893 for val in inst.allValues():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
894 if opmap[val] is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
895 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
896 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
897 self.needFlagCoalesce = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
898 self.needFlagDisperse = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
899 self.lastOp = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
900 opmap[val] = inst.generateName(val)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
901 bodymap[val] = inst.generateBody(val, self, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
902
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
903 pieces.append('\nstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
904 for inst in range(0, len(opmap)):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
905 op = opmap[inst]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
906 if op is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
907 pieces.append('\n\tunimplemented,')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
908 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
909 pieces.append('\n\t' + op + ',')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
910 body.append(bodymap[inst])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
911 pieces.append('\n};')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
912 if self.body in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
913 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
914 pieces.append('\n{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
915 pieces.append('\n\twhile (context->current_cycle < target_cycle)')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
916 pieces.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
917 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
918 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
919 self.subroutines[self.body].inline(self, [], pieces, otype, None)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
920 pieces.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
921 pieces.append('\n}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
922 return ''.join(body) + ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
923
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
924 def checkBool(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
925 if not name in self.booleans:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
926 raise Exception(name + ' is not a defined boolean flag')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
927 return self.booleans[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
928
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
929 def getTemp(self, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
930 if size in self.temp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
931 return ('', self.temp[size])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
932 self.temp[size] = 'tmp{sz}'.format(sz=size);
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
933 return ('\n\tuint{sz}_t tmp{sz};'.format(sz=size), self.temp[size])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
934
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
935 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
936 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
937 while keepGoing:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
938 keepGoing = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
939 try:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
940 if type(param) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
941 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
942 elif param.startswith('0x'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
943 param = int(param, 16)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
944 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
945 param = int(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
946 except ValueError:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
947
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
948 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
949 if param in parent.regValues and allowConstant:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
950 return parent.regValues[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
951 maybeLocal = parent.resolveLocal(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
952 if maybeLocal:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
953 return maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
954 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
955 param = fieldVals[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
956 elif param in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
957 param = self.meta[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
958 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
959 elif self.isReg(param):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
960 param = self.resolveReg(param, parent, fieldVals, isdst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
961 return param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
962
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
963 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
964 if not type(name) is str:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
965 return False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
966 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
967 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
968 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
969 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
970 return self.regs.isRegArray(begin)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
971 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
972 return self.regs.isReg(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
973
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
974 def resolveReg(self, name, parent, fieldVals, isDst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
975 begin,sep,end = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
976 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
979 if not self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980 end = self.resolveParam(end, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
981 if not type(end) is int and self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
982 arrayName = self.regs.arrayMemberParent(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
983 end = self.regs.arrayMemberIndex(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
984 if arrayName != begin:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
985 end = 'context->{0}[{1}]'.format(arrayName, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
986 regName = self.regs.arrayMemberName(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
987 ret = 'context->{0}[{1}]'.format(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
988 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
989 regName = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
990 if self.regs.isRegArrayMember(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
991 arr,idx = self.regs.regToArray[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
992 ret = 'context->{0}[{1}]'.format(arr, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
993 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
994 ret = 'context->' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
995 if regName == self.flags.flagReg:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
996 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
997 self.needFlagDisperse = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
998 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
999 self.needFlagCoalesce = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1000 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1001 self.lastDst = regName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1002 return ret
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1003
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1004
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1005
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1006 def paramSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1007 size = self.currentScope.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1008 if size:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1009 return size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1010 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1011 if sep and self.regs.isRegArray(begin):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1012 return self.regs.regArrays[begin][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1013 if self.regs.isReg(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1014 return self.regs.regs[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1015 return 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1016
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1017 def parse(f):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 instructions = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1019 subroutines = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1020 registers = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1021 flags = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1022 errors = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1023 info = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1024 line_num = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1025 cur_object = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1026 for line in f:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1027 line_num += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1028 line,_,comment = line.partition('#')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1029 if not line.strip():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1030 continue
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1031 if line[0].isspace():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1032 if not cur_object is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1033 parts = [el.strip() for el in line.split(' ')]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1034 if type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1035 cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1036 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1037 cur_object = cur_object.processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1038
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1039 # if type(cur_object) is Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1040 # if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1041 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1042 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1043 # cur_object.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1044 # elif type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1045 # cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1046 # elif parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1047 # o = Switch(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1048 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1049 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1050 # elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1051 # o = If(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1052 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1053 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1054 # elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1055 # cur_object = cur_object.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1056 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1057 # cur_object.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 errors.append("Orphan instruction on line {0}".format(line_num))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1061 parts = line.split(' ')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 if len(parts) > 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1064 table,bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1065 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1066 bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1067 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1068 value = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1069 fields = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1070 curbit = len(bitpattern) - 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1071 for char in bitpattern:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1072 value <<= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1073 if char in ('0', '1'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1074 value |= int(char)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1075 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1076 if char in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1077 fields[char] = (curbit, fields[char][1] + 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1078 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1079 fields[char] = (curbit, 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1080 curbit -= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1081 cur_object = Instruction(value, fields, name.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1082 instructions.setdefault(table, []).append(cur_object)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1083 elif line.strip() == 'regs':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1084 if registers is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1085 registers = Registers()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1086 cur_object = registers
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1087 elif line.strip() == 'info':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1088 cur_object = info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1089 elif line.strip() == 'flags':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1090 if flags is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1091 flags = Flags()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 cur_object = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1093 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1094 cur_object = SubRoutine(line.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1095 subroutines[cur_object.name] = cur_object
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1096 if errors:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1097 print(errors)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1098 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1099 p = Program(registers, instructions, subroutines, info, flags)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1100 p.booleans['dynarec'] = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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1101 p.booleans['interp'] = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1102
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1103 print('#include "m68k_prefix.c"')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1104 print(p.build('c'))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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1105
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1106 def main(argv):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1107 f = open(argv[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1108 parse(f)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1109
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1110 if __name__ == '__main__':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1111 from sys import argv
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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1112 main(argv)