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annotate svp.cpu @ 1614:c9639139aedf

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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
author Michael Pavone <pavone@retrodev.com>
date Fri, 21 Sep 2018 09:26:12 -0700
parents 2d9e8a7b8ba2
children 28f80d1b343e
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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1 info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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2 prefix svp_
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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3 opcode_size 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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4 body svp_run_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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6 regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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7 internal 16 scratch1 x y scratch2 st pad pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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8 a 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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9 stack 16 stack0 stack1 stack2 stack3 stack4 stack5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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10 stackidx 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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11 p 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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12 external 16 pm0 pm1 pm2 xst pm4 ext5 pmc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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13 pointers0 8 r0 r1 r2 r3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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14 pointers1 8 r4 r5 r6 r7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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15 iram 16 1024
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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16 ram0 16 256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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17 ram1 16 256
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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18 zflag 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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19 nflag 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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20 rpl 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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21
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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22 flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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23 register st
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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24 Z 13 zero zflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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25 N 15 sign nflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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26 R 0-2 none rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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27
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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28 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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29 mov stack.stackidx dst
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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30 add 1 stackidx stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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31 switch stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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32 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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33 mov 0 stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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34 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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35
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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36 svp_push
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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37 arg src 16
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38 add -1 stackidx stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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39 switch stackidx
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40 case -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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41 mov 5 stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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42 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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43 mov src stack.stackidx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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44
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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45 svp_ram_read
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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46 arg mode 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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47 arg banki 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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48 arg regi 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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49 local idx 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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50
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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51 switch banki
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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52 case 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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53 meta bank ram0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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54 meta reg pointers0.regi
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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55
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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56 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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57 meta bank ram1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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58 meta reg pointers1.regi
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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59 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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60
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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61 mov reg idx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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62 switch mode
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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63 case 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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64 meta modestr ""
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65
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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66 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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67 meta modestr +!
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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68 add 1 reg reg
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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69
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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70 case 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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71 #loop decremenet
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72 meta modestr -
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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73 mov reg tmp
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
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74
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
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75 if rpl
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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76 lsl 1 rpl rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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77 sub 1 rpl rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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78 local mask 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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79 not rpl mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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80 and reg mask reg
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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81 sub 1 tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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82 and rpl tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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83 or rpl reg reg
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
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84 else
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
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85 sub 1 reg reg
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
86 end
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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87
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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88 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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89 #loop increment
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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90 meta modestr +
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91
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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92 and 7 st rpl
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
93 if rpl
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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94 mov reg tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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95 lsl 1 rpl rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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96 sub 1 rpl rpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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97 local mask 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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98 not rpl mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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99 and reg mask reg
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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100 add 1 tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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101 and rpl tmp tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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102 or rpl reg reg
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
103 else
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
104 sub 1 reg reg
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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105 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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106
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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107 and 255 idx idx
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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108 meta val bank.idx
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109
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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110 svp_read_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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111 arg regidxr 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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112 switch regidxr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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113 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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114 meta val a
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115
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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116 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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117 #TODO: PMAR stuff
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118 meta val external.regidxr
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119 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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120
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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121 svp_write_ext
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122 arg regidxw 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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123 switch regidxw
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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124 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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125 and 0xFFFF0000 a a
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126 or src a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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127
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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128 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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129 #TODO: PMAR stuff
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff changeset
130 mov src external.regidxw
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
131 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 svp_alu_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134 arg P 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 arg param 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137 switch P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139 dis "sub %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 sub param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 dis "cmp %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 cmp param a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 case 4
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 dis "add %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 add param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 dis "and %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 and param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 dis "or %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156 or param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159 dis "eor %s" name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 xor param a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 svp_check_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 arg fval 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 arg cond 16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 local invert 8
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 switch cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 case 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 meta flag 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 meta flag zflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 meta flag nflag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 meta flag 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 end
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
181
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
182 if fval
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
183 meta istrue flag
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
184
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
185 else
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 lnot flag invert
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
187 meta istrue invert
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191 PPP0000000000000 alu_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194 meta name "-"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 svp_alu_op P 0xFFFF0000
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 PPP0000000000RRR alu_r
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201 lsl internal.R 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202 meta name internal.R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 PPP0000000000011 alu_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 svp_alu_op P a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 PPP0000000000101 alu_stack
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 meta name "st"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 PPP0000000000111 alu_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 meta name p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 svp_alu_op P p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 PPP0000000001RRR alu_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 svp_read_ext R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 meta name val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 PPP0001B000MMRR alu_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 svp_ram_read M B R
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 switch P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 case 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 dis "sub (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 sub tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 dis "cmp (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 cmp tmp a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 case 4
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 dis "add (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 add tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 case 5
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 dis "and (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 and tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 dis "or (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 dis "eor (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 xor tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 PPP0000000001111 alu_al
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 invalid P 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 invalid P 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 lsl a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 meta name al
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 svp_alu_op P tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 1001000FCCCC0OOO cond_mod
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 svp_check_cond F C
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
280 if istrue
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
281
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 switch O
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 case 2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 asr a 1 a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 case 3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 lsl a 1 a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 case 6
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 neg a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 update_flags ZN
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 abs a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 update_flags N
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 end
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
299 end
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 000000000DDD0SSS ld_int_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 dis "ld %s, %s" internal.D internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 mov internal.S internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 000000000DDD0101 ld_int_st
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 dis "ld %s, st" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 meta dst internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 0000000000110101 ld_a_st
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 dis "ld a, st"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 lsl tmp 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 0000000001110101 ld_p_st
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 dis "ld p, st"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 meta dst tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 svp_pop
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 lsl tmp 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 0000000001010SSS ld_st_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 dis "ld st, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 svp_push internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 0000000001010011 ld_st_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 dis "ld st, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 svp_push tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 0000000001010111 ld_st_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 dis "ld st, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 svp_push tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 0000000000000000 ld_n1_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 #nop?
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 dis "ld -, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 0000000000000SSS ld_n1_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 #nop?
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 dis "nop??"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 0000000000110111 ld_a_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 dis "ld a, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 mov p a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 0000000001110011 ld_p_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 dis "ld p, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 mov a p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 0000000000110011 ld_a_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 dis "ld a, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 mov a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 0000000001110111 ld_p_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 dis "ld p, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 mov p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 000000000DDD0111 ld_int_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 mov tmp internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 dis "ld %s, p" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 000000000DDD0111 ld_int_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 mov tmp internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 dis "ld %s, a" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 0000000001110SSS ld_p_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 lsl internal.S 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 mov tmp p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 dis "ld p, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 0000000000110SSS ld_a_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 lsl internal.S 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 mov tmp a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 dis "ld a, %s" internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 000000000DDD0000 ld_int_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 dis "ld %s, -" internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 mov 0xFFFF internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 0000000000110000 ld_a_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 dis "ld a, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 or 0xFFFF0000 a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 0000000001110000 ld_p_n1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 dis "ld p, -"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 or 0xFFFF0000 p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 000000000DDD1SSS ld_int_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 dis "ld %s, %s" internal.D val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 mov val internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 0000000000111SSS ld_a_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 dis "ld a, %s" val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 0000000001111SSS ld_p_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 dis "ld p, %s" val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 000000001DDD0SSS ld_ext_int
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 meta src internal.S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 dis "ld al, %s" src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 dis "ld %s, %s" external.D src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 000000001DDD0011 ld_ext_a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 lsr a 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 meta src tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 dis "ld al, a"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 dis "ld %s, a" external.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 000000001DDD0111 ld_ext_p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 lsr p 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 meta src tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 dis "ld al, p"
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 dis "ld %s, p" external.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 000000001DDD1SSS ld_ext_ext
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 svp_read_ext S
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 meta src val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 svp_write_ext D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 switch D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 case 7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 dis "ld al, %s" src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 default
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 dis "ld %s, %s" external.D src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 0000001B0DDDMMPP ld_int_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 dis "ld %s, (%s%s)" internal.D reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 mov val internal.D
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 0000001B0011MMPP ld_a_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 dis "ld a, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 and 0xFFFF a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 or tmp a a
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 0000001B0111MMPP ld_p_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 dis "ld p, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 local tmp 32
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 lsl val 16 tmp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 and 0xFFFF p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 or tmp p p
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 0000001B0101MMPP ld_st_ram
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 svp_ram_read M B P
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 dis "ld st, (%s%s)" reg modestr
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 svp_push val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 0100100FCCCC0000 call_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 svp_check_cond F C
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
506 if istrue
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 svp_push pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 mov scratch1 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 0100110FCCCC0000 bra_cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 svp_check_cond F C
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 svp_op_fetch
1614
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Michael Pavone <pavone@retrodev.com>
parents: 1613
diff changeset
514 if istrue
1613
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 mov scratch1 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 cycles 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 cmp 1024 pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 if >=U
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 mov pc scratch1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 add scratch1 scratch1 scratch1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 ocall read_16
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 else
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 mov iram.pc scratch1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 end
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 add 1 pc pc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 svp_run_op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 svp_op_fetch
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 dispatch scratch1