Mercurial > repos > blastem

annotate m68k.cpu @ 2448:d1eec03dca09

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix some issues in new 68K core and add implementations of negx and clr instructions
author Michael Pavone <pavone@retrodev.com>
date Thu, 15 Feb 2024 21:49:17 -0800
parents 7d4df6b74263
children 6c93869babc1
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 info
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2 prefix m68k_
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
3 opcode_size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
4 body m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
5 header m68k.h
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
6 interrupt m68k_interrupt
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
7 include m68k_util.c
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
8 sync_cycle m68k_sync_cycle
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
9
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
10 declare
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
11 typedef m68k_context *(*sync_fun)(m68k_context * context, uint32_t address);
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
12 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
13 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
14 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun sync_components, int_ack_fun int_ack);
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
15 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler reset_handler);
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
16 void m68k_reset(m68k_context *context);
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
17 void m68k_print_regs(m68k_context *context);
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
18
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
19 regs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
20 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
21 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
22 pc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
23 other_sp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
24 scratch1 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
25 scratch2 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
26 int_cycle 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
27 prefetch 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
28 int_priority 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
29 int_num 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
30 int_pending 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
31 int_pending_num 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
32 int_ack 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
33 status 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
34 ccr 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
35 xflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
36 nflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
37 zflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
38 vflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
39 cflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
40 reset_handler ptrvoid
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
41 mem_pointers ptrvoid 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
42
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
43 flags
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
44 register ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
45 X 4 carry xflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
46 N 3 sign nflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
47 Z 2 zero zflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
48 V 1 overflow vflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
49 C 0 carry cflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
50
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
51 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
52 if dynarec
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
53
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
54 ccall m68k_read16_noinc context pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
55 mov result prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
56
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
57 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
58
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
59 if interp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
60
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
61 mov pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
62 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
63 mov scratch1 prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
64
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
65 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
66
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
67 add 2 pc pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
68
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
69 check_user_mode_swap_ssp_usp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
70 local tmp 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
71 and 0x20 status tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
72 if tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
73 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
74
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
75 xchg other_sp a7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
76
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
77 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
78
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
79 m68k_get_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
80 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
81 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
82
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
83 m68k_write32_lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
84 arg value 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
85 add 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
86 mov value scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
87 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
88
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
89 sub 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
90 lsr value 16 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
91 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
92
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
93 m68k_write32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
94 arg value 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
95 local tmp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
96 mov value tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
97 lsr value 16 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
98 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
99
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
100 add 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
101 mov tmp scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
102 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
103
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
104 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
105 local tmp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
106 add 2 scratch1 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
107 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
108 xchg scratch1 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
109 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
110 lsl tmp 16 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
111 or tmp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
112
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
113 m68k_interrupt
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
114 cmp int_cycle cycles
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
115 if >=U
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
116
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
117 #INT_PENDING_NONE
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
118 cmp 255 int_pending
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
119 if =
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
120
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
121 mov int_priority int_pending
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
122 mov int_num int_pending_num
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
123
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
124 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
125
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
126 #INT_PENDING_SR_CHANGE
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
127 cmp 254 int_pending
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
128 if =
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
129
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
130 mov int_priority int_pending
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
131 mov int_num int_pending_num
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 check_user_mode_swap_ssp_usp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137 cycles 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 #save status reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139 sub 6 a7 a7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 m68k_get_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141 mov a7 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 #update status register
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145 and 0x78 status status
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 or int_priority status status
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 or 0x20 status status
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149 #Interrupt ack cycle
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
150 mov int_pending int_ack
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 if int_pending_num
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 cycles 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 #TODO: do the whole E clock variable latency nonsense
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 cycles 13
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156 add 24 int_pending int_pending_num
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159 #save pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 add 2 a7 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 m68k_write32_lowfirst pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 lsl int_pending_num 2 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 mov scratch1 pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 update_sync
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 dispatch prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 m68k_mem_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 arg address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 mov address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 mov address scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 meta ismem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
184 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 m68k_write_size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 arg lowfirst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 ocall write_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 if lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 m68k_write32_lowfirst scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209 m68k_write32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 local disp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 and prefetch 255 disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 sext 16 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 sext 32 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 local index 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 lsr prefetch 12 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 local isareg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 and index 8 isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 and index 7 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 local islong 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 and prefetch 2048 islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 switch isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 sext 32 dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 mov dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 case 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 sext 32 aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 mov aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 add disp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 m68k_fetch_op_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 #data reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 meta op dregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 #address reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 meta op aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 #address reg indirect
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 #postincrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 addsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 #predecrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 decsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 cycles 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 #displacement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 add scratch1 aregs.reg scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 #indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
309 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 add aregs.reg scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 #pc-relative and absolute modes
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 #absolute short
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 #absolute long
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 local address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 lsl prefetch 16 address
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 or prefetch address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 #pc displaceent
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 add scratch1 pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 #pc indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
343 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 add pc scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 #immediate
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 local tmp32 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 lsl prefetch 16 tmp32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 or prefetch tmp32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 mov prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 m68k_fetch_src_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 m68k_fetch_op_ea mode reg Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 meta src op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 meta src_is_mem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 m68k_fetch_dst_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 m68k_fetch_op_ea mode reg Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 meta dst op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 m68k_save_dst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 if ismem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 1101DDD0ZZMMMRRR add_ea_dn
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 m68k_fetch_src_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 add src dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 1101DDD1ZZMMMRRR add_dn_ea
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
408 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
409 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 add dregs.D dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 1101AAAZ11MMMRRR adda
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 local size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 local ext_src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 m68k_fetch_src_ea M R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 sext 32 src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 meta src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 add src aregs.A aregs.A
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 00000110ZZMMMRRR addi
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 local immed 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 invalid Z 3
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
448 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 #fetch immediate operand
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 lsl prefetch 16 immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 or prefetch immed immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 mov prefetch immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 #fetch dst EA
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 add immed dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 0101III0ZZMMMRRR addq
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 local src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 switch I
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 mov 8 src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 mov I src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 case 1
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
492 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 1101DDD1ZZ000SSS addx_dy_dx
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 adc dregs.S dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 1101DDD1ZZ001SSS addx_ay_ax
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 switch S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 sub 2 aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 mov aregs.S scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 mov scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 switch D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 sub 2 aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 mov aregs.D scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 adc scratch2 scratch1 scratch1 Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 mov aregs.D scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
589
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
590 1100DDD0ZZMMMRRR and_ea_dn
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
591 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
592 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
593 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
594 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
595 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
596 m68k_fetch_src_ea M R Z
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
598 and src dregs.D dregs.D Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
599 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
600 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
601
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
602 1100DDD1ZZMMMRRR and_dn_ea
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
603 invalid M 0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
604 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
605 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
606 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
607 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
608 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
609 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
610 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
611 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
612 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
613
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
614 and dregs.D dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
615 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
616 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
617 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
618
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
619 00000010ZZMMMRRR andi
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
620 local immed 32
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
621 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
622 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
623 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
624 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
625 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
626 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
627 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
628 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
629 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
630 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
631 switch Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
632 case 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
633 lsl prefetch 16 immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
634 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
635 or prefetch immed immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
636 default
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
637 mov prefetch immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
638 end
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
639 #fetch dst EA
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
640 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
641
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
642 and immed dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
643 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
644 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
645 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
646
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
647 0000001000111100 andi_to_ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
648 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
649 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
650 and prefetch ccr ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
651 m68k_prefetch
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
652
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
653 1011DDD1ZZMMMRRR eor_dn_ea
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
654 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
655 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
656 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
657 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
658 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
659 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
660 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
661 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
662 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
663
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
664 xor dregs.D dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
665 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
666 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
667 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
668
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
669 00001010ZZMMMRRR eori
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
670 local immed 32
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
671 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
672 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
673 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
674 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
675 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
676 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
677 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
678 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
679 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
680 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
681 switch Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
682 case 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
683 lsl prefetch 16 immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
684 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
685 or prefetch immed immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
686 default
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
687 mov prefetch immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
688 end
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
689 #fetch dst EA
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
690 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
691
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
692 xor immed dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
693 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
694 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
695 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
696
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
697 0000001000111100 eori_to_ccr
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
698 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
699 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
700 xor prefetch ccr ccr
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
701 m68k_prefetch
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
702
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
703 1000DDD0ZZMMMRRR or_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
704 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
705 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
706 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
707 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
708 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
709 m68k_fetch_src_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
710
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
711 or src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
712 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
713 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
714
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
715 1000DDD1ZZMMMRRR or_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
716 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
717 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
718 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
719 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
720 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
721 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
722 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
723 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
724 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
725 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
726
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
727 or dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
728 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
729 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
730 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
731
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
732 00000000ZZMMMRRR ori
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
733 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
734 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
735 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
736 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
737 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
738 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
739 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
740 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
741 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
742 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
743 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
744 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
745 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
746 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
747 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
748 or prefetch immed immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
749 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
750 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
751 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
752 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
753 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
754
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
755 or immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
756 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
757 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
758 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
759
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
760 0000000000111100 ori_to_ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
761 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
762 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
763 or prefetch ccr ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
764 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
765
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
766 1001DDD0ZZMMMRRR sub_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
767 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
768 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
769 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
770 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
771 m68k_fetch_src_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
772
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
773 sub src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
774 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
775 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
776
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
777 1001DDD1ZZMMMRRR sub_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
778 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
779 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
780 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
781 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
782 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
783 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
784 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
785 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
786 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
787 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
788
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
789 sub dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
790 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
791 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
792 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
793
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
794 1001AAAZ11MMMRRR suba
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
795 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
796 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
797 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
798 local size 16
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
799 local ext_src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
800 if Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
801 mov 2 size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
802 else
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
803 mov 1 size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
804 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
805 m68k_fetch_src_ea M R size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
806 switch size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
807 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
808 sext 32 src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
809 meta src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
810 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
811
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
812 sub src aregs.A aregs.A
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
813 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
814
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
815 00000100ZZMMMRRR subi
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
816 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
817 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
818 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
819 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
820 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
821 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
822 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
823 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
824 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
825 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
826 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
827 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
828 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
829 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
830 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
831 or prefetch immed immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
832 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
833 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
834 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
835 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
836 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
837
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
838 sub immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
839 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
840 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
841 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
842
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
843 0101III1ZZMMMRRR subq
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
844 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
845 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
846 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
847 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
848 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
849 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
850 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
851 local src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
852 switch I
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
853 case 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
854 mov 8 src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
855 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
856 mov I src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
857 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
858
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
859 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
860 switch M
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
861 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
862 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
863 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
864 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
865 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
866 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
867 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
868 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
869
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
870 1110CCC0ZZ001RRR lsri
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
871 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
872 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
873 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
874 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
875 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
876 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
877 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
878 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
879 update_flags XNZV0C
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
880 local cyc 32
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
881 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
882 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
883 case 2
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
884 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
885 default
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
886 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
887 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
888 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
889 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
890 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
891
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
892 1110CCC0ZZ101RRR lsr_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
893 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
894 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
895 and dregs.C 63 shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
896 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
897 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
898 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
899 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
900 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
901 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
902 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
903 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
904 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
905 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
906 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
907 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
908
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
909 1110001011MMMRRR lsr_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
910 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
911 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
912 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
913 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
914 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
915 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
916 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
917 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
918
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
919 m68k_fetch_dst_ea M R 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
920 lsr dst 1 dst
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
921 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
922 m68k_save_dst 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
923 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
924
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
925 1110CCC1ZZ001RRR lsli
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
926 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
927 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
928 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
929 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
930 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
931 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
932 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
933 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
934 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
935 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
936 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
937 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
938 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
939 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
940 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
941 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
942 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
943 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
944 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
945
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
946 1110CCC1ZZ101RRR lsl_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
947 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
948 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
949 and dregs.C 63 shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
950 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
951 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
952 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
953 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
954 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
955 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
956 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
957 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
958 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
959 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
960 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
961 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
962
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
963 1110001111MMMRRR lsl_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
964 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
965 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
966 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
967 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
968 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
969 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
970 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
971 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
972
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
973 m68k_fetch_dst_ea M R 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
974 lsl dst 1 dst
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
975 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
976 m68k_save_dst 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
977 m68k_prefetch
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
979 00ZZRRRMMMEEESSS move
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
981 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
982 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
983 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
984 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
985 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
986 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
987 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
988 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
989 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
990 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
991 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
992 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
993 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
994 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
995 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
996 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
997 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
998
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
999 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1000 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1001 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1002 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1003 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1004
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1005 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1006 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1007
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1008 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1009 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1010 mov src dregs.R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1011
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1012 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1013 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1014 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1015 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1016
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1017 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1018 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1019 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1020 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1021 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1022 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1023 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1024 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1025 addsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1026 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1027 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1028 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1029 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1030 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1031
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1032 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1033 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1034 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1035 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1036 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1037 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1038 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1039 decsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1040 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1041 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1042 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1043 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1044 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1045 m68k_write_size size 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1046
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1047 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1048 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1049 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1050 add aregs.R scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1051 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1052 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1053
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1054 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1055 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1056 add aregs.R scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1057 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1059 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1061
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1062
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 00ZZ00M111EEESSS move_abs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1064 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1065 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1066 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1067 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1068 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1069 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1070 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1071 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1072 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1073 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1074 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1075 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1076 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1077 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1078 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1079 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1080
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1081 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1082 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1083 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1084 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1085 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1086
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1087 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1088 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1089
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1090 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1091 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1093 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1094
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1095 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1096 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1097 lsl prefetch 16 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1098 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1099 or prefetch scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1100 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1101 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1102 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1103 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1104
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1105 00ZZRRR001EEESSS movea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1106 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1107 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1108 invalid Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1109 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1110 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1111 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1112 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1113 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1114 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1115 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1116 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1117 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1118 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1119 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1120 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1121 mov src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1122 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1123 sext 32 src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1124 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1125 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1126
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1127 0100010011MMMRRR move_to_ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1128 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1129 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1130 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1131 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1132 m68k_fetch_src_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1133 mov scratch1 ccr
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1134 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1135 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1136
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1137 0100011011MMMRRR move_to_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1138 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1139 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1140 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1141 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1142 m68k_fetch_src_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1143 mov scratch1 ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1144 lsr scratch1 8 status
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1145 update_sync
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1146 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1147 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1148
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 0100000011MMMRRR move_from_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1150 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1151 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1152 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1153 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1154 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1155 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1156 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1157 m68k_fetch_dst_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1158 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1159 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1160 mov scratch1 dst
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1161 if M
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1162 cycles 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1163 else
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1164 cycles 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1165 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1166 m68k_save_dst 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1168
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1169 01000000ZZMMMRRR negx
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1170 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1171 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1172 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1173 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1174 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1175 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1176 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1177 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1178 sbc dst 0 dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1179 update_flags XNZVC
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1180 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1181 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1182
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1183 01000010ZZMMMRRR clr
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1184 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1185 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1186 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1187 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1188 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1189 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1190 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1191 invalid Z 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1192 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1193 dst:Z = 0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1194 update_flags N0Z1V0C0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1195 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1196 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1197
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1198 0100111001110000 reset
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1199 if reset_handler
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1200 pcall reset_handler m68k_reset_handler context
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1201 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1202 cycles 128
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1203 m68k_prefetch