annotate test.s68 @ 989:d70000fdff0b

Implemented IR and undefined bits of info word for address error exception frames
author Michael Pavone <pavone@retrodev.com>
date Wed, 27 Apr 2016 21:39:17 -0700
parents 3adbd97f71f2
children
rev   line source
pavone@45 1 dc.l $0, start
pavone@45 2 dc.l start
pavone@45 3 dc.l start
pavone@45 4 dc.l start
pavone@45 5 dc.l start
pavone@45 6 dc.l start
pavone@45 7 dc.l start
pavone@45 8 dc.l start
pavone@45 9 dc.l start
pavone@45 10 dc.l start
pavone@45 11 dc.l start
pavone@45 12 dc.l start
pavone@45 13 dc.l start
pavone@45 14 dc.l start
pavone@45 15 dc.l start
pavone@45 16 dc.l start
pavone@45 17 dc.l start
pavone@45 18 dc.l start
pavone@45 19 dc.l start
pavone@45 20 dc.l start
pavone@45 21 dc.l start
pavone@45 22 dc.l start
pavone@45 23 dc.l start
pavone@45 24 dc.l after
pavone@45 25 dc.l after
pavone@45 26 dc.l after
pavone@45 27 dc.l after
pavone@45 28 dc.l after
pavone@45 29 dc.l after
pavone@45 30 dc.l after
pavone@45 31 dc.l after
pavone@45 32
pavone@45 33 start:
pavone@45 34 bra after
pavone@45 35 after:
pavone@12 36 abcd d0, d1
pavone@12 37 abcd -(a2), -(a3)
pavone@12 38 add.b #42, d1
pavone@12 39 add.w d3, d4
pavone@12 40 add.l d5, (a0)+
pavone@12 41 addq.w #5, d0
pavone@12 42 addx d6, d7
pavone@12 43 addx -(a4), -(a5)
pavone@12 44 and.w d5, d7
pavone@12 45 andi.l #5, (a0)+
pavone@12 46 andi #8, CCR
pavone@12 47 andi #9, CCR
pavone@12 48 foo:
pavone@12 49 asl d0, d3
pavone@12 50 asr #3, d7
pavone@12 51 bne foo
pavone@12 52 bchg #5, d0
pavone@12 53 bclr #7, d0
pavone@12 54 bset #1, d0
pavone@12 55 bsr bar
pavone@12 56 btst #3, d0
pavone@12 57 chk.w #53, d7
pavone@12 58 clr d5
pavone@12 59 cmp d0, d1
pavone@12 60 bar:
pavone@12 61 dbra d0, bar
pavone@12 62 divs.w d5, d7
pavone@12 63 divu.w d3, d4
pavone@12 64 eor.w d0, d6
pavone@12 65 eori.l #5, d2
pavone@12 66 eori #5, ccr
pavone@12 67 eori #2700, sr
pavone@12 68 exg d5, d6
pavone@12 69 ext d2
pavone@12 70 illegal
pavone@12 71 jmp (a0)
pavone@12 72 jsr (a5)
pavone@12 73 lea (a0, 8), a3
pavone@12 74 link.w a6, #32
pavone@12 75 lsl d0, d3
pavone@12 76 lsr #3, d7
pavone@12 77 move.b (a0)+, (32, a5)
pavone@12 78 moveq #5, d0
pavone@12 79 move #89, ccr
pavone@12 80 move sr, d0
pavone@12 81 move #2700, sr
pavone@12 82 move a5, usp
pavone@12 83 movem.l d0-d3/a4/a6, -(a7)
pavone@12 84 movep.w d4, (40, a3)
pavone@12 85 muls.w d6, d7
pavone@12 86 mulu.w d2, d4
pavone@12 87 nbcd -(a2)
pavone@12 88 neg.l d7
pavone@12 89 negx.b d5
pavone@12 90 nop
pavone@12 91 not.b d3
pavone@12 92 or.w d5, d7
pavone@12 93 ori.b #7, d5
pavone@12 94 ori #5, ccr
pavone@12 95 ori #2700, sr
pavone@12 96 pea (24, a3)
pavone@12 97 reset
pavone@12 98 rol.l #7, d0
pavone@12 99 rol.w d5, d0
pavone@12 100 ror.w d1, d3
pavone@12 101 roxl.l #7, d0
pavone@12 102 roxl.w d5, d0
pavone@12 103 roxr.w d1, d3
pavone@12 104 rte
pavone@12 105 rtr
pavone@12 106 rts
pavone@12 107 sbcd d0, d1
pavone@12 108 sbcd -(a2), -(a3)
pavone@12 109 slt d5
pavone@12 110 stop #3
pavone@12 111 sub.b #42, d1
pavone@12 112 sub.w d3, d4
pavone@12 113 sub.l d5, (a0)+
pavone@12 114 subq.w #5, d0
pavone@12 115 subx d6, d7
pavone@12 116 subx -(a4), -(a5)
pavone@12 117 swap d6
pavone@12 118 tas (a3)
pavone@12 119 trap #7
pavone@12 120 trapv
pavone@12 121 tst.w (a4)+
pavone@12 122 unlk a6
pavone@12 123