annotate upd78k2.cpu @ 2707:a64c0e1ed6ac default tip

Implement speed control and reset for media player. Fix other bindings that could cause it to crash
author Michael Pavone <pavone@retrodev.com>
date Sun, 06 Jul 2025 20:43:37 -0700
parents 0bd48217941a
children
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1 #"Minimum instruction cycle is 333 ns for internal ROM 500 ns for external at 12 MHz"
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2 #That's 4 clks for internal ROM, 6 clocks external
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3 #Above seems to be defined based on external clock input, but there's an internal divider
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4 #Instruction timing tables seem to specified in terms of this divided clock
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5 info
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6 prefix upd78k2_
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7 opcode_size 8
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8 header upd78k2.h
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9 body upd78k2_run_op
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10 sync_cycle upd78k2_sync_cycle
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11 extra_tables sfr bit1 bit2 muldiv base sfrbit spmov indexed regind alt_base alt_indexed alt_regind mov_reg
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12 include upd78k2_util.c
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13 regs
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14 main 8 x a c b e d l h
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15 psw 8
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16 pc 16
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17 sp 16
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18 rbs 8
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19 int_enable 8
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20 int_priority_flag 8
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21 chflags 8
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22 zflag 8
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23 stbc 8
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24 int_cycle 32
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25 scratch1 32
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26 scratch2 32
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27 mem_pointers ptr8 4
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28 port_data 8 8
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29 port_mode 8 8
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30 mm 8
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31 if0 16
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32 mk0 16
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33 pr0 16
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34 ism0 16
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35 intm0 8
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36 intm1 8
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37 ist 8
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38 iram 8 256
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39 flags
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40 register psw
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41 I 7 none int_enable
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42 Z 6 zero zflag
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43 R 5 none rbs.1
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44 A 4 half-carry chflags.3
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45 B 3 none rbs.0
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46 P 1 none int_priority_flag
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47 C 0 carry chflags.7
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48 declare
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49 uint8_t upd78237_sfr_read(uint32_t address, void *context);
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50 void *upd78237_sfr_write(uint32_t address, void *context, uint8_t value);
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51 void init_upd78k2_opts(upd78k2_options *opts, memmap_chunk const *chunks, uint32_t num_chunks);
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52 upd78k2_context *init_upd78k2_context(upd78k2_options *opts);
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53 void upd78k2_sync_cycle(upd78k2_context *upd, uint32_t target_cycle);
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54
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55 #Prefix bytes
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56 # 0000 0001 -> saddr becomes sfr, mem becomes &mem
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57 # 0000 0010 -> bit instructions/ conditional branches
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58 # 0000 0011 -> more bit instructions / conditional branches
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59 # 0000 0110 -> base mode
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60 # 0000 1000 -> saddr/sfr bit instructions / conditional branches
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61 # 0000 1001 -> mov !addr16/stbc
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62 # 0000 1010 -> indexed mode
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63 # 0001 0110 -> register indirect
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64
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65 sfr_read
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66 arg offset 8
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67 scratch1 = offset + 0xFF00
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68 ocall read_8
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69
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70 sfr_write
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71 arg offset 8
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72 arg value 8
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73 scratch2 = offset + 0xFF00
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74 scratch1 = value
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75 ocall write_8
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76
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77 iram_read
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78 arg offset 8
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79 local normal_iram 8
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80 normal_iram = 1
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81 if offset >=U 0xE0
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82 #register bank area
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83 switch rbs
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84 case 0
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85 if offset >=U 0xF8
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86 normal_iram = 0
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87 end
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88 case 1
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89 if offset >=U 0xF0
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90 if offset >=U 0xF8
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91 else
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92 normal_iram = 0
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93 end
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94 end
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95 case 2
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96 if offset >=U 0xE8
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97 if offset >=U 0xF0
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98 else
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99 normal_iram = 0
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100 end
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101 end
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102 case 3
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103 if offset >=U 0xE8
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104 else
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105 normal_iram = 0
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106 end
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107 end
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108 end
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109 if normal_iram
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110 scratch1 = iram.offset
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111 else
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112 scratch1 = offset & 7
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113 scratch1 = main.scratch1
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114 end
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115
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116 iram_write
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117 arg offset 8
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118 arg value 8
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119 local normal_iram 8
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120 local regnum 8
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121 normal_iram = 1
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122 if offset >=U 0xE0
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123 #register bank area
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124 switch rbs
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125 case 0
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126 if offset >=U 0xF8
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127 normal_iram = 0
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128 end
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129 case 1
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130 if offset >=U 0xF0
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131 if offset >=U 0xF8
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132 else
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133 normal_iram = 0
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134 end
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135 end
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136 case 2
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137 if offset >=U 0xE8
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138 if offset >=U 0xF0
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139 else
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140 normal_iram = 0
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141 end
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142 end
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143 case 3
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144 if offset >=U 0xE8
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145 else
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146 normal_iram = 0
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147 end
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148 end
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149 end
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diff changeset
150 if normal_iram
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
151 iram.offset = value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
152 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
153 regnum = offset & 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
154 main.regnum = value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
155 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
156
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
157 mem_read_no_exp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
158 arg addr 32
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
159 local offset 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
160 if addr >=U 0xFE00
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161 if addr >=U 0xFF00
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 offset = addr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 sfr_read offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165 offset = addr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 iram_read offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 scratch1 = addr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 ocall read_8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173 mem_write_no_exp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 arg addr 32
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 arg value 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176 local offset 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 if addr >=U 0xFE00
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 if addr >=U 0xFF00
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 offset = addr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 sfr_write offset value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182 offset = addr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183 iram_write offset value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
184 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 scratch2 = addr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187 scratch1 = value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188 ocall write_8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192 mem_read_no_exp pc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 pc += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 upd78k2_op_fetch_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 local tmp 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 tmp = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 scratch1 <<= 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201 scratch1 |= tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203 upd78k2_run_op
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 dispatch scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 saddr_read
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208 arg offset 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209 local tmp 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 if offset >=U 0xE0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 #sfr area
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 tmp = offset - 0xE0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213 sfr_read tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 tmp = offset + 0x20
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 iram_read tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 saddr_write
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 arg offset 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 arg value 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 local tmp 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 if offset >=U 0xE0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 #sfr area
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 tmp = offset - 0xE0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 sfr_write tmp value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 tmp = offset + 0x20
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 iram_write tmp value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 mem_read
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 arg address 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 local full_address 32
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 local meg_enable 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 meg_enable = mm & 0x40
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 if meg_enable
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 if alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 full_address = port_data.6 & 0xF
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 full_address = port_mode.6 & 0xF
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 full_address <<= 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 full_address |= address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 full_address = address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 mem_read_no_exp full_address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 mem_write
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 arg address 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 arg value 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 local full_address 32
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 local meg_enable 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 meg_enable = mm & 0x40
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 if meg_enable
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 if alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 full_address = port_data.6 & 0xF
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 full_address = port_mode.6 & 0xF
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 full_address <<= 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 full_address |= address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 full_address = address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 mem_write_no_exp full_address value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 push_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 arg value 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 local tmp 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 tmp = value >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 sp -= 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 mem_write_no_exp sp tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 tmp = value
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 sp -= 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 mem_write_no_exp sp tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 pop_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 mem_read_no_exp sp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 dst = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 sp += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 mem_read_no_exp sp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 scratch1 <<= 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 dst |= scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 sp += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 00000000 nop
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 cycles 2 #minimum cycle time appears to be 4 (ignoring internal divider)
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 00000001 sfr_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 dispatch scratch1 sfr
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 00000010 bit1_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 dispatch scratch1 bit1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 00000011 bit2_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 dispatch scratch1 bit2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 00000101 muldiv_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 dispatch scratch1 muldiv
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 00000110 base_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 dispatch scratch1 base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 00001000 sfrbit_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 dispatch scratch1 sfrbit
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 00001001 spmov_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 dispatch scratch1 spmov
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 00001010 indexed_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 dispatch scratch1 indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 00010110 regind_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 dispatch scratch1 regind
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 00100100 mov_reg_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 dispatch scratch1 mov_reg
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 sfr 00000110 alt_base_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 dispatch scratch1 alt_base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 sfr 00001010 alt_indexed_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 dispatch scratch1 alt_indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 sfr 00010110 alt_regind_prefix
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 dispatch scratch1 alt_regind
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 aluop
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 arg op 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 arg src 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 switch op
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 case 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 dst += src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 case 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 adc dst src dst
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 case 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 dst -= src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 case 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 sbc dst src dst
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 case 4
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 dst &= src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 update_flags Z
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 case 5
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 dst ^= src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 update_flags Z
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 case 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 dst |= src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 update_flags Z
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 case 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 cmp dst src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 aluop16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 arg op 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 arg src 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 switch op
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 case 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 dst += src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 case 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 dst -= src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 case 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 dst -= src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 update_flags ZAC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 default
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 #TODO: what happens in these invalid cases
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 10001PPP alu_r_r
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 local tmp_src 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 local tmp_dst 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 scratch2 = scratch1 >> 4
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 if scratch2 >=U 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 #TODO: is MSB just ignored or is this treated as some kind of illegal instruction or nop?
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 scratch1 &= 0xF
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 if scratch1 >=U 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 scratch1 &= 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 meta dst tmp_dst
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 tmp_dst = a << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 tmp_dst |= x
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 switch scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 case 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 tmp_src = a << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 tmp_src |= x
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 case 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 tmp_src = b << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 tmp_src |= c
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 case 4
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 tmp_src = d << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 tmp_src |= e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 case 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 tmp_src = h << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 tmp_src |= l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 default
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 #TODO: what happens in these invalid cases
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 aluop16 P tmp_src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 x = tmp_dst
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 a = tmp_dst >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 meta dst main.scratch2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 cycles 2 #penalty for extra IRAM access since regs are technically stored there?
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 aluop P main.scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 10101PPP alu_immed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 aluop P scratch1
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
436
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
437 01101PPP alu_saddr_immed
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
438 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
439 local immed 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
440 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
441 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
442 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
443 immed = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
444 saddr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
445 meta dst scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
446 aluop P immed
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
447 saddr_write offset scratch1
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 calc_addr_base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 arg regpair 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 local tmp 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 switch regpair
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 case 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 #[de+byte]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 tmp = d << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 tmp |= e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 adst += tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 case 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 #[sp+byte]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 adst += sp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 case 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 #[hl+byte]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 tmp = h << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 tmp |= l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 adst += tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 read_base_mode
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 arg regpair 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 meta adst scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 calc_addr_base regpair
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 mem_read scratch1 alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 write_base_mode
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 arg regpair 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 arg value 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 meta adst scratch2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 calc_addr_base regpair
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 mem_write scratch2 value alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 calc_addr_regind
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 arg regpair 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 local tmp 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 switch regpair
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 case 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 #[de+]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 adst = d << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 adst |= e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 tmp = adst + 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 e = tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 d = tmp >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 case 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 #[hl+]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 adst = h << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 adst |= l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 tmp = adst + 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 l = tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 h = tmp >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 case 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 #[de-]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 adst = d << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 adst |= e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 tmp = adst - 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 e = tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 d = tmp >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 case 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 #[hl-]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 adst = h << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 adst |= l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 tmp = adst - 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 l = tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 h = tmp >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 case 4
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 #[de]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 adst = d << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 adst |= e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 case 5
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 #[hl]
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 adst = h << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 adst |= l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 read_regind_mode
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 arg regpair 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 meta adst scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 calc_addr_regind regpair
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 mem_read scratch1 alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 write_regind_mode
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 arg regpair 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 arg value 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 meta adst scratch2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 calc_addr_regind regpair
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 mem_write scratch2 value alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 calc_addr_indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 arg index_reg 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 local tmp 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 upd78k2_op_fetch_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 switch index_reg
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 case 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 tmp = d << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 tmp |= e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 adst += tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 case 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 adst += a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 case 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 tmp = h << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 tmp |= l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 adst += tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 case 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 adst += b
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 read_indexed_mode
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 arg index_reg 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 meta adst scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 calc_addr_indexed index_reg
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 mem_read scratch1 alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 write_indexed_mode
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 arg index_reg 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 arg value 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 arg alt_bank 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 meta adst scratch2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 calc_addr_indexed index_reg
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 mem_write scratch2 value alt_bank
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 base 00RR1PPP alu_base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 invalid R 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 read_base_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 aluop P scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 alt_base 00RR1PPP alu_alt_base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 invalid R 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583 read_base_mode R 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 aluop P scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587 base 00RR0000 mov_a_base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 invalid R 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 read_base_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
590 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
591
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
592 alt_base 00RR0000 alt_mov_a_base
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
593 invalid R 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594 read_base_mode R 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597 base 10RR0000 mov_base_a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598 invalid R 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 write_base_mode R a 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601 alt_base 10RR0000 alt_mov_base_a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 invalid R 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 write_base_mode R a 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 regind 0RRR1PPP alu_reg_indirect
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 read_regind_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 aluop P scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 alt_regind 0RRR1PPP alu_alt_reg_indirect
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 read_regind_mode R 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 aluop P scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 regind 0RRR0000 mov_a_reg_indirect
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 read_regind_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 alt_regind 0RRR0000 alt_mov_a_reg_indirect
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 read_regind_mode R 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 regind 1RRR0000 mov_reg_indirect_a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 write_regind_mode R a 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 alt_regind 1RRR0000 alt_mov_reg_indirect_a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 write_regind_mode R a 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 01010RRR mov_reg_indirect_a_short
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 write_regind_mode R a 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 01011RRR mov_a_reg_indirect_short
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 invalid R 6
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 invalid R 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 read_regind_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 indexed 00RR1PPP alu_indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 read_indexed_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 aluop P scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 alt_indexed 00RR1PPP alu_alt_indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 read_indexed_mode R 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 meta dst a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 aluop P scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 indexed 00RR0000 mov_a_indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 read_indexed_mode R 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 alt_indexed 00RR0000 alt_mov_a_indexed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 read_indexed_mode R 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 a = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 indexed 10RR0000 mov_indexed_a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 write_indexed_mode R a 0
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 alt_indexed 10RR0000 alt_mov_indexed_a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 write_indexed_mode R a 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 mov_reg 0DD01SS0 movw_rp_rp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 local dst 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 local src 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 dst = D << 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 src = S << 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 main.dst = main.src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 dst += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 src += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 main.dst = main.src
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 mov_reg 0DDD0SSS mov_r_r
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 main.D = main.S
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 01100PP0 movw_rp_immed
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 local dst 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691 dst = P << 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 main.dst = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 dst += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 main.dst = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
698 10111RRR mov_r_immed
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
699 local dst 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
700 dst = R << 1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
701 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
702 main.dst = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
703
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
704 spmov 11000000 mov_stbc_immed
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
705 local tmp 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
706 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
707 tmp = ~scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
708 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
709 if tmp = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
710 stbc = tmp
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
711 #TODO: actually handle stbc changes
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
712 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
713
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
714 spmov 11110000 mov_a_abs
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
715 upd78k2_op_fetch_word
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
716 mem_read_no_exp scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
717 a = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
718
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
719 spmov 11110001 mov_abs_a
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
720 upd78k2_op_fetch_word
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
721 scratch2 = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
722 mem_write_no_exp scratch2 a
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
723
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
724 11000RRR inc_r
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
725 cycles 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
726 main.R += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
727 update_flags ZA
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729 11001RRR dec_r
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
730 cycles 2
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731 main.R -= 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732 update_flags ZA
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 11010RRR mov_a_r
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
735 a = main.R
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
736
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
737 muldiv 01001PP0 br_rp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
738 local reg 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
739 local tmp 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
740 reg = P << 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
741 pc = main.reg
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
742 reg += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
743 tmp = main.reg << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
744 pc |= tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
745
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
746 00010100 br_rel
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
747 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
748 sext 16 scratch1 scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
749 pc += scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
750
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
751 00101100 br_abs
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
752 upd78k2_op_fetch_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753 pc = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
755 100000FS bcc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756 local flag 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
758 if F
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
759 flag = chflags >> 7
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
760 else
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
761 flag = zflag
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
762 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
763 if flag = S
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
764 sext 16 scratch1 scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
765 pc += scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
766 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
767
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
768 bit1 10100BBB bf_psw
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
769 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
770 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
771 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
772 mask &= psw
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
773 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
774 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
775 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
776 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
777
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
778 bit1 10110BBB bt_psw
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
779 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
780 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
781 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
782 mask &= psw
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
783 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
784 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
785 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
786 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
787
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
788 bit2 1010RBBB bf_r
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
789 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
790 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
791 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
792 mask &= main.R
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
793 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
794 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
795 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
796 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
797
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
798 bit2 1011RBBB bt_r
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
799 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
800 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
801 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
802 mask &= main.R
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
803 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
804 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
805 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
806 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
807
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
808 sfrbit 10100BBB bf_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
809 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
810 local tmp 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
811 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
812 saddr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
813 tmp = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
814 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
815 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
816 mask &= tmp
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
817 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
818 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
819 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
820 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
821
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
822 01110BBB bt_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
823 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
824 local tmp 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
825 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
826 saddr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
827 tmp = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
828 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
829 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
830 mask &= tmp
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
831 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
832 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
833 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
834 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
835
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
836 sfrbit 10101BBB bf_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
837 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
838 local tmp 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
839 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
840 sfr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
841 tmp = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
842 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
843 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
844 mask &= tmp
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
845 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
846 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
847 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
848 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
849
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
850 sfrbit 10111BBB bt_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
851 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
852 local tmp 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
853 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
854 sfr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
855 tmp = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
856 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
857 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
858 mask &= tmp
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
859 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
860 sext 16 scratch1 scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
861 pc += scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
862 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
863
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
864 muldiv 01011PP0 call_rp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
865 local reg 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
866 local tmp 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
867 push_word pc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
868 reg = P << 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
869 pc = main.reg
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
870 reg += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
871 tmp = main.reg << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
872 pc |= tmp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
873
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
874 00101000 call_long
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
875 local address 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
876 upd78k2_op_fetch_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
877 address = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
878 push_word pc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
879 pc = address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
880
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
881 10010AAA call_short
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
882 local address 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
883 address = A << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
884 address |= 0x800
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
885 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
886 address |= scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
887 push_word pc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
888 pc = address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
889
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
890 111TTTTT call_table
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
891 local address 16
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
892 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
893 offset = T << 1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
894 offset += 0x40
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
895 mem_read_no_exp T
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
896 address = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
897 scratch1 = T + 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
898 mem_read_no_exp scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
899 scratch1 <<= 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
900 address |= 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
901 push_word pc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
902 pc = address
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
903
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
904 01001010 di
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
905 int_enable = 0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
906 update_sync
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
907
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
908 01001011 ei
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
909 int_enable = 1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
910 update_sync
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
911
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
912 if cycles >=U int_cycle
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
913 int_cycle = cycles + 1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
914 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
915
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
916
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
917 01010110 ret
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
918 meta dst pc
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
919 pop_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
920
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
921 001101PP pop_rp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
922 local rp 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
923 local word 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
924 meta dst word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
925 pop_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
926 main.rp = word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
927 rp += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
928 main.rp = word >> 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
929
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
930 001111PP push_rp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
931 local rp 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
932 local word 16
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
933 rp = P << 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
934 rp += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
935 word = main.rp << 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
936 rp -= 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
937 word |= main.rp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
938 push_word word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
939
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
940 muldiv 101010NN sel
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
941 local offset 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
942 if N != rbs
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
943 offset = rbs << 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
944 offset = 0xF8 - offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
945 iram.offset = x
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
946 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
947 iram.offset = a
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
948 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
949 iram.offset = c
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
950 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
951 iram.offset = b
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
952 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
953 iram.offset = e
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
954 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
955 iram.offset = d
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
956 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
957 iram.offset = l
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
958 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
959 iram.offset = h
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
960 offset = N << 3
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
961 offset = 0xF8 - offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
962 x = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
963 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
964 a = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
965 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
966 c = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
967 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
968 b = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
969 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
970 e = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
971 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
972 d = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
973 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
974 l = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
975 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
976 h = iram.offset
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977 rbs = N
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
979
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980 muldiv 11001000 incw_sp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
981 sp += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
982
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
983 muldiv 11001001 decw_sp
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
984 sp -= 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
985
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
986 00001011 movw_sfrp_immed
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
987 local offset 8
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
988 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
989 if scratch1 = 0xFC
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
990 #unclear if SP is actually mapped in the SFR space
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
991 #or if this is special cased, but the docs don't
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
992 #suggest you can write to SP with other SFR-targeting
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
993 #instructions so I'm assuming the latter.
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
994 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
995 sp = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
996 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
997 scratch1 <<= 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
998 sp |= scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
999 else
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1000 offset = scratch1
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1001 upd78k2_op_fetch
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1002 sfr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1003 offset += 1
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1004 upd78k2_op_fetch
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1005 sfr_write offset scratch1
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1006 end
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1007
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1008 00001100 movw_sadrp_word
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1009 local offset 8
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1010 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1011 offset = scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1012 upd78k2_op_fetch
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1013 saddr_write offset scratch1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1014 offset += 1
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1015 upd78k2_op_fetch
2706
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1016 saddr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1017
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1018 00101011 mov_sfr_immed
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1019 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1020 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1021 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1022 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1023 if offset = 0xFE
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1024 psw = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1025 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1026 sfr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1027 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1028
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1029 00111010 mov_saddr_immed
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1030 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1031 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1032 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1033 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1034 saddr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1035
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1036 sfrbit 00000BBB mov1_cy_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1037 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1038 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1039 saddr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1040 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1041 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1042 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1043 update_flags C0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1044 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1045 update_flags C1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1046 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1047
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1048 sfrbit 00001BBB mov1_cy_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1049 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1050 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1051 sfr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1052 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1053 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1054 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1055 update_flags C0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1056 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1057 update_flags C1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1058 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1059
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1060 sfrbit 00010BBB mov1_saddr_cy
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1061 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1062 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1063 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1064 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1065 saddr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1066 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1067 if chflags >=U 0x80
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1068 scratch1 |= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1069 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1070 mask = ~mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1071 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1072 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1073 saddr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1074
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1075 sfrbit 00011BBB mov1_sfr_cy
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1076 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1077 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1078 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1079 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1080 sfr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1081 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1082 if chflags >=U 0x80
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1083 scratch1 |= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1084 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1085 mask = ~mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1086 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1087 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1088 sfr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1089
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1090 sfrbit 001I0BBB and1_cy_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1091 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1092 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1093 saddr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1094 if I
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1095 scratch1 = ~scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1096 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1097 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1098 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1099 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1100 update_flags C0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1101 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1102
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1103 sfrbit 001I1BBB and1_cy_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1104 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1105 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1106 sfr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1107 if I
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1108 scratch1 = ~scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1109 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1110 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1111 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1112 if =
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1113 update_flags C0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1114 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1115
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1116 sfrbit 010I0BBB or1_cy_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1117 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1118 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1119 saddr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1120 if I
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1121 scratch1 = ~scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1122 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1123 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1124 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1125 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1126 update_flags C1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1127 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1128
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1129 sfrbit 010I1BBB or1_cy_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1130 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1131 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1132 sfr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1133 if I
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1134 scratch1 = ~scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1135 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1136 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1137 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1138 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1139 update_flags C1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1140 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1141
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1142 sfrbit 01100BBB xor1_cy_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1143 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1144 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1145 saddr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1146 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1147 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1148 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1149 if chflags >=U 0x80
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1150 update_flags C0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1151 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1152 update_flags C1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1153 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1154 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1155
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1156 sfrbit 01101BBB xor1_cy_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1157 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1158 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1159 sfr_read scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1160 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1161 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1162 if !=
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1163 if chflags >=U 0x80
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1164 update_flags C0
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1165 else
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1166 update_flags C1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1167 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1168 end
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1169
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1170 sfrbit 01110BBB not1_saddr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1171 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1172 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1173 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1174 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1175 saddr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1176 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1177 scratch1 ^= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1178 saddr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1179
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1180 sfrbit 01111BBB not1_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1181 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1182 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1183 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1184 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1185 sfr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1186 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1187 scratch1 ^= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1188 sfr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1189
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1190 sfrbit 10001BBB set1_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1191 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1192 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1193 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1194 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1195 sfr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1196 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1197 scratch1 |= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1198 sfr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1199
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1200 sfrbit 10011BBB clr1_sfr
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1201 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1202 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1203 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1204 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1205 sfr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1206 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1207 mask = ~mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1208 scratch1 &= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1209 sfr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1210
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1211 10110BBB set1_saddr_cy
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1212 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1213 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1214 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1215 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1216 saddr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1217 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1218 scratch1 |= mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1219 saddr_write offset scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1220
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1221 10100BBB clr1_saddr_cy
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1222 local mask 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1223 local offset 8
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1224 upd78k2_op_fetch
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1225 offset = scratch1
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1226 saddr_read offset
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1227 mask = 1 << B
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1228 mask = ~mask
0bd48217941a Get uPD78K/II core done enough to run the LaserActive firmware main loop
Michael Pavone <pavone@retrodev.com>
parents: 2705
diff changeset
1229 scratch1 &= mask
2705
ab2d916380bf WIP uPD78K/II CPU core
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1230 saddr_write offset scratch1