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annotate runtime.S @ 71:f80fa1776507

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Implement more instructions and address modes
author Mike Pavone <pavone@retrodev.com>
date Fri, 21 Dec 2012 01:00:52 -0800
parents 7a22a0e6c004
children 7935cd64d5c8
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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17
de0085d4ea40 Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1
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2 .global handle_cycle_limit
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3 handle_cycle_limit:
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4 call m68k_save_context
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5 mov %rsi, %rdi
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6 call sync_components
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7 mov %rax, %rsi
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8 call m68k_load_context
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9 ret
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10
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11 do_vdp_port_write:
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12 call m68k_save_context
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13 mov %rcx, %rdx
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14 call vdp_port_write
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15 mov %rax, %rsi
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16 call m68k_load_context
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17 ret
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18
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19 do_vdp_port_read:
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bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
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20 mov %ecx, %edi
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21 call m68k_save_context
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22 call vdp_port_read
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23 mov %rax, %rsi
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24 call m68k_load_context
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25 mov 120(%rsi), %cx
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26 ret
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27
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28 do_io_write:
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29 call m68k_save_context
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30 and $0xFF, %edi
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31 mov %rcx, %rdx
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32 call io_write
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33 mov %rax, %rsi
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34 call m68k_load_context
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35 ret
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36 do_io_read:
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37 mov %ecx, %edi
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38 and $0xFF, %edi
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39 call m68k_save_context
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40 call io_read
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41 mov %rax, %rsi
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42 call m68k_load_context
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43 mov 120(%rsi), %cl
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44 ret
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45
54
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46 bad_access_msg:
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47 .asciz "Program tried to access illegal 68K address %X\n"
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48
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49 .global m68k_write_word
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50 .global try_fifo_write
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51 m68k_write_word:
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52 call inccycles
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53 and $0xFFFFFF, %rdi
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54 cmp $0x400000, %edi
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55 jle cart_w
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56 cmp $0xE00000, %edi
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57 jge workram_w
54
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58 cmp $0xC00000, %edi
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59 jge vdp_psg_w
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60 ret
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61 workram_w:
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62 and $0xFFFF, %rdi
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63 mov %cx, (%r9, %rdi)
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64 ret
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65 cart_w:
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66 mov %cx, (%r8, %rdi)
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67 ret
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68 vdp_psg_w:
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69 test $0x2700E0, %edi
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70 jnz crash
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71 and $0x1F, %edi
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72 cmp $4, %edi
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73 jl try_fifo_write
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74 jmp do_vdp_port_write
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75 try_fifo_write:
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76 push %rdx
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77 push %rbx
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78 /* fetch VDP context pointer from 68K context */
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79 mov 112(%rsi), %rdx
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80 /* get fifo_cur and compare it to fifo_end */
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81 mov (%rdx), %rbx
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82 cmp %rbx, 8(%rdx)
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83 /* bail out if fifo is full */
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84 je fifo_fallback
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85 /* populate FIFO entry */
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86 mov %cx, 4(%rbx) /* value */
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87 movb $0, 6(%rbx) /* partial */
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88 mov %eax, %ecx
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89 shl $3, %ecx /* multiply by 68K cycle by 7 to get MCLK cycle */
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90 sub %eax, %ecx
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91 mov %ecx, (%rbx) /* cycle */
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92 /* update fifo_cur and store back in 68K context */
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93 add $8, %rbx
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94 mov %rbx, (%rdx)
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95 /* clear pending flag */
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96 andb $0xEF, 19(%rdx)
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97 pop %rbx
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98 pop %rdx
64
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99 ret
54
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100 fifo_fallback:
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101 pop %rbx
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102 pop %rdx
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103 jmp do_vdp_port_write
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104 crash:
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105 mov %edi, %esi
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106 lea bad_access_msg(%rip), %rdi
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107 call printf
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108 mov $1, %rdi
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109 call exit
18
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110
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111 .global m68k_write_byte
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112 m68k_write_byte:
64
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113 call inccycles
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114 and $0xFFFFFF, %rdi
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115 /* deal with byte swapping */
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116 xor $1, %edi
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117 cmp $0x400000, %edi
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118 jle cart_wb
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119 cmp $0xE00000, %edi
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120 jge workram_wb
66
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121 cmp $0xC00000, %edi
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122 jge vdp_psg_wb
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123 cmp $0xA10000, %edi
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124 jl not_io_wb
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125 cmp $0xA10100, %edi
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126 jge not_io_wb
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127 jmp do_io_write
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128 not_io_wb:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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129 ret
18
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130 workram_wb:
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131 and $0xFFFF, %rdi
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132 mov %cl, (%r9, %rdi)
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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133 ret
18
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134 cart_wb:
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135 mov %cl, (%r8, %rdi)
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
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136 ret
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
137 vdp_psg_wb:
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
138 push %rdx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
139 mov %cl, %dl
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
140 and $0xFF, %cx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
141 shl $8, %dx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
142 or %dx, %cx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
143 pop %rdx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
144 jmp vdp_psg_w
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
145
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
146 .global m68k_write_long_lowfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
147 m68k_write_long_lowfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
148 push %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
149 add $2, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
150 call m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
151 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
152 pop %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
153 jmp m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
154
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
155 .global m68k_write_long_highfirst
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
156 m68k_write_long_highfirst:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
157 push %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
158 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
159 shr $16, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
160 call m68k_write_word
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
161 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
162 pop %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
163 add $2, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
164 jmp m68k_write_word
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
165
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
166 inccycles:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
167 cmp %rbp, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
168 jge do_limit
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
169 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
170 ret
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
171 do_limit:
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
172 push %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
173 push %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
174 call handle_cycle_limit
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
175 pop %rdi
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
176 pop %rcx
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
177 add $4, %rax
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
178 ret
17
de0085d4ea40 Add asssembly runtime code stub
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
179
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
180 .global m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
181 m68k_read_word_scratch1:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
182 call inccycles
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
183 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
184 cmp $0x400000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
185 jle cart
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
186 cmp $0xE00000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
187 jge workram
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
188 cmp $0xC00000, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
189 jge vdp_psg
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
190 xor %cx, %cx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
191 dec %cx
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
192 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
193 workram:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
194 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
195 mov (%r9, %rcx), %cx
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
196 ret
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
197 vdp_psg:
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
198 test $0x2700E0, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
199 jnz crash
57
bc3bc7a60c4e Code in runtime for checking for VDP reads was using the wrong register. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
200 and $0x1F, %ecx
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
201 jmp do_vdp_port_read
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
202 cart:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
203 mov (%r8, %rcx), %cx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
204 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
205
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
206 .global m68k_read_long_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
207 m68k_read_long_scratch1:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
208 push %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
209 call m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
210 mov %cx, %di
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
211 pop %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
212 add $2, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
213 call m68k_read_word_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
214 and $0xFFFF, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
215 shl $16, %edi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
216 or %edi, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
217 ret
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
218
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
219 .global m68k_read_byte_scratch1
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
220 m68k_read_byte_scratch1:
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
221 call inccycles
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
222 and $0xFFFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
223 /* deal with byte swapping */
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
224 xor $1, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
225 cmp $0x400000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
226 jle cart_b
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
227 cmp $0xE00000, %ecx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
228 jge workram_b
66
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
229 cmp $0xA10000, %ecx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
230 jl not_io_b
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
231 cmp $0xA10100, %ecx
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
232 jge not_io_b
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
233 jmp do_io_read
7a22a0e6c004 Gamepad support
Mike Pavone <pavone@retrodev.com>
parents: 64
diff changeset
234 not_io_b:
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
235 xor %cl, %cl
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 53
diff changeset
236 dec %cl
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
237 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
238 workram_b:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
239 and $0xFFFF, %rcx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
240 mov (%r9, %rcx), %cl
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
241 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
242 cart_b:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
243 mov (%r8, %rcx), %cl
64
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Mike Pavone <pavone@retrodev.com>
parents: 59
diff changeset
244 ret
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
245
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
246 ret_addr_msg:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
247 .asciz "Program modified return address on stack: found %X, expected %X\n"
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
248
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
249 .global m68k_modified_ret_addr
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
250 m68k_modified_ret_addr:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
251 lea ret_addr_msg(%rip), %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
252 mov %rcx, %rsi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
253 mov 8(%rsp), %rdx
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
254 call printf
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
255 mov $1, %rdi
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
256 call exit
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
diff changeset
257
53
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
258 dyn_addr_msg:
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
259 .asciz "Program needs dynamically calculated native address\n"
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
260
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
261 .global m68k_native_addr
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
262 m68k_native_addr:
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
263 lea dyn_addr_msg(%rip), %rdi
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
264 call puts
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
265 mov $1, %rdi
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
266 call exit
44e661913a51 Add preliminary support for JMP
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
267
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 17
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268 .global m68k_save_context
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269 m68k_save_context:
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parents: 17
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270 mov %bl, 1(%rsi) /* N Flag */
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parents: 17
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271 mov %bh, 2(%rsi) /* V flag */
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parents: 17
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272 mov %dl, 3(%rsi) /* Z flag */
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parents: 17
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273 mov %dh, 4(%rsi) /* C flag */
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parents: 17
diff changeset
274 mov %r10d, 8(%rsi) /* d0 */
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parents: 17
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275 mov %r11d, 12(%rsi) /* d1 */
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parents: 17
diff changeset
276 mov %r12d, 16(%rsi) /* d2 */
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parents: 17
diff changeset
277 mov %r13d, 40(%rsi) /* a0 */
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parents: 17
diff changeset
278 mov %r14d, 44(%rsi) /* a1 */
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279 mov %r15d, 68(%rsi) /* a7 */
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
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parents: 53
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280 mov %eax, 76(%rsi) /* current cycle count */
18
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281 ret
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282
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283 .global m68k_load_context
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284 m68k_load_context:
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parents: 17
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285 mov 1(%rsi), %bl /* N Flag */
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parents: 17
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286 mov 2(%rsi), %bh /* V flag */
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parents: 17
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287 mov 3(%rsi), %dl /* Z flag */
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parents: 17
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288 mov 4(%rsi), %dh /* C flag */
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parents: 17
diff changeset
289 mov 8(%rsi), %r10d /* d0 */
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parents: 17
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290 mov 12(%rsi), %r11d /* d1 */
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parents: 17
diff changeset
291 mov 16(%rsi), %r12d /* d2 */
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parents: 17
diff changeset
292 mov 40(%rsi), %r13d /* a0 */
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parents: 17
diff changeset
293 mov 44(%rsi), %r14d /* a1 */
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parents: 17
diff changeset
294 mov 68(%rsi), %r15d /* a7 */
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parents: 17
diff changeset
295 mov 72(%rsi), %ebp /* target cycle count */
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parents: 17
diff changeset
296 mov 76(%rsi), %eax /* current cycle count */
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parents: 17
diff changeset
297 mov 80(%rsi), %r8d /* cartridge address */
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parents: 17
diff changeset
298 mov 88(%rsi), %r9d /* work ram address */
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parents: 17
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299 ret
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300
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parents: 17
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301 .global m68k_start_context
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302 m68k_start_context:
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303 call m68k_load_context
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304 jmp *%rdi