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comparison cpu_dsl.py @ 1753:33ec5df77fac

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Integration of new Z80 core is sort of working now
author Michael Pavone <pavone@retrodev.com>
date Tue, 12 Feb 2019 09:58:04 -0800
parents d6d4c006a7b3
children 043cf458704c
comparison
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1752:d6d4c006a7b3 1753:33ec5df77fac
694 ), 694 ),
695 'cmp': Op().addImplementation('c', None, _cmpCImpl), 695 'cmp': Op().addImplementation('c', None, _cmpCImpl),
696 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl), 696 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
697 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( 697 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
698 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) 698 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
699 )), 699 ) + _updateSyncCImpl(prog, params)),
700 'cycles': Op().addImplementation('c', None, 700 'cycles': Op().addImplementation('c', None,
701 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( 701 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
702 params[0] 702 params[0]
703 ) 703 )
704 ), 704 ),