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diff cpu_dsl.py @ 1753:33ec5df77fac

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Integration of new Z80 core is sort of working now
author Michael Pavone <pavone@retrodev.com>
date Tue, 12 Feb 2019 09:58:04 -0800
parents d6d4c006a7b3
children 043cf458704c
line wrap: on
line diff
--- a/cpu_dsl.py	Sun Feb 10 11:58:23 2019 -0800
+++ b/cpu_dsl.py	Tue Feb 12 09:58:04 2019 -0800
@@ -696,7 +696,7 @@
 	'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
 	'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
 		pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
-	)),
+	) + _updateSyncCImpl(prog, params)),
 	'cycles': Op().addImplementation('c', None,
 		lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
 			params[0]