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comparison cpu_dsl.py @ 2441:4435abe5db5e

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Sugar for binary operators in CPU DSL
author Michael Pavone <pavone@retrodev.com>
date Sun, 11 Feb 2024 20:15:00 -0800
parents 338c78da3fff
children 52cfc7b14dd2
comparison
equal deleted inserted replaced
2440:338c78da3fff 2441:4435abe5db5e
8 '>>=': 'lsr', 8 '>>=': 'lsr',
9 '&=': 'and', 9 '&=': 'and',
10 '|=': 'or', 10 '|=': 'or',
11 '^=': 'xor' 11 '^=': 'xor'
12 } 12 }
13 binaryOps = {
14 '+': 'add',
15 '-': 'sub',
16 '<<': 'lsl',
17 '>>': 'lsr',
18 '&': 'and',
19 '|': 'or',
20 '^': 'xor'
21 }
13 class Block: 22 class Block:
14 def addOp(self, op): 23 def addOp(self, op):
15 pass 24 pass
16 25
17 def processLine(self, parts): 26 def processLine(self, parts):
28 else: 37 else:
29 if len(parts) > 1 and parts[1] in assignmentOps: 38 if len(parts) > 1 and parts[1] in assignmentOps:
30 dst = parts[0] 39 dst = parts[0]
31 op = parts[1] 40 op = parts[1]
32 parts = [assignmentOps[op]] + parts[2:] 41 parts = [assignmentOps[op]] + parts[2:]
33 if op != '=': 42 if op == '=':
43 if len(parts) > 2 and parts[2] in binaryOps:
44 op = parts[2]
45 parts[0] = binaryOps[op]
46 del parts[2]
47 else:
34 if op == '<<=' or op == '>>=': 48 if op == '<<=' or op == '>>=':
35 parts.insert(1, dst) 49 parts.insert(1, dst)
36 else: 50 else:
37 parts.append(dst) 51 parts.append(dst)
38 parts.append(dst) 52 parts.append(dst)