diff cpu_dsl.py @ 2441:4435abe5db5e

Sugar for binary operators in CPU DSL
author Michael Pavone <pavone@retrodev.com>
date Sun, 11 Feb 2024 20:15:00 -0800
parents 338c78da3fff
children 52cfc7b14dd2
line wrap: on
line diff
--- a/cpu_dsl.py	Sun Feb 11 17:26:52 2024 -0800
+++ b/cpu_dsl.py	Sun Feb 11 20:15:00 2024 -0800
@@ -10,6 +10,15 @@
 	'|=': 'or',
 	'^=': 'xor'
 }
+binaryOps = {
+	'+': 'add',
+	'-': 'sub',
+	'<<': 'lsl',
+	'>>': 'lsr',
+	'&': 'and',
+	'|': 'or',
+	'^': 'xor'
+}
 class Block:
 	def addOp(self, op):
 		pass
@@ -30,7 +39,12 @@
 				dst = parts[0]
 				op = parts[1]
 				parts = [assignmentOps[op]] + parts[2:]
-				if op != '=':
+				if op == '=':
+					if len(parts) > 2 and parts[2] in binaryOps:
+						op = parts[2]
+						parts[0] = binaryOps[op]
+						del parts[2]
+				else:
 					if op == '<<=' or op == '>>=':
 						parts.insert(1, dst)
 					else: