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Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
author Mike Pavone <pavone@retrodev.com>
date Fri, 13 Sep 2013 19:22:46 -0700
parents 5f3344d0d42f
children f065769836e8
comparison
equal deleted inserted replaced
469:5f3344d0d42f 470:541c1ae8abf3
360 } else { 360 } else {
361 printf("Illegal write to HV Counter port %X\n", vdp_port); 361 printf("Illegal write to HV Counter port %X\n", vdp_port);
362 exit(1); 362 exit(1);
363 } 363 }
364 if (v_context->cycles != before_cycle) { 364 if (v_context->cycles != before_cycle) {
365 //printf("68K paused for %d (%d) cycles at cycle %d (%d)\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle); 365 printf("68K paused for %d (%d) cycles at cycle %d (%d) for write\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle);
366 context->current_cycle = v_context->cycles / MCLKS_PER_68K; 366 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
367 } 367 }
368 } else if (vdp_port < 0x18) { 368 } else if (vdp_port < 0x18) {
369 genesis_context * gen = context->system; 369 genesis_context * gen = context->system;
370 sync_sound(gen, context->current_cycle * MCLKS_PER_68K); 370 sync_sound(gen, context->current_cycle * MCLKS_PER_68K);
400 } 400 }
401 } else if (vdp_port < 0x18) { 401 } else if (vdp_port < 0x18) {
402 sync_sound(gen, context->current_cycle * MCLKS_PER_Z80); 402 sync_sound(gen, context->current_cycle * MCLKS_PER_Z80);
403 psg_write(gen->psg, value); 403 psg_write(gen->psg, value);
404 } else { 404 } else {
405 //TODO: Implement undocumented test register(s) 405 vdp_test_port_write(gen->vdp, value);
406 } 406 }
407 return context; 407 return context;
408 } 408 }
409 409
410 uint16_t vdp_port_read(uint32_t vdp_port, m68k_context * context) 410 uint16_t vdp_port_read(uint32_t vdp_port, m68k_context * context)
415 } 415 }
416 vdp_port &= 0x1F; 416 vdp_port &= 0x1F;
417 uint16_t value; 417 uint16_t value;
418 sync_components(context, 0); 418 sync_components(context, 0);
419 vdp_context * v_context = context->video_context; 419 vdp_context * v_context = context->video_context;
420 uint32_t before_cycle = v_context->cycles;
420 if (vdp_port < 0x10) { 421 if (vdp_port < 0x10) {
421 if (vdp_port < 4) { 422 if (vdp_port < 4) {
422 value = vdp_data_port_read(v_context); 423 value = vdp_data_port_read(v_context);
423 } else if(vdp_port < 8) { 424 } else if(vdp_port < 8) {
424 value = vdp_control_port_read(v_context); 425 value = vdp_control_port_read(v_context);
425 } else { 426 } else {
426 value = vdp_hv_counter_read(v_context); 427 value = vdp_hv_counter_read(v_context);
427 //printf("HV Counter: %X at cycle %d\n", value, v_context->cycles); 428 //printf("HV Counter: %X at cycle %d\n", value, v_context->cycles);
428 } 429 }
430 } else if (vdp_port < 0x18){
431 printf("Illegal read from PSG port %X\n", vdp_port);
432 exit(1);
429 } else { 433 } else {
430 printf("Illegal read from PSG or test register port %X\n", vdp_port); 434 value = vdp_test_port_read(v_context);
431 exit(1); 435 }
436 if (v_context->cycles != before_cycle) {
437 printf("68K paused for %d (%d) cycles at cycle %d (%d) for read\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle);
438 context->current_cycle = v_context->cycles / MCLKS_PER_68K;
432 } 439 }
433 return value; 440 return value;
434 } 441 }
435 442
436 uint8_t vdp_port_read_b(uint32_t vdp_port, m68k_context * context) 443 uint8_t vdp_port_read_b(uint32_t vdp_port, m68k_context * context)