diff blastem.c @ 470:541c1ae8abf3

Properly delay 68K on VDP reads. Dummy VDP test port implementation. Initial stab at handling undefined bits of VSRAM and CRAM.
author Mike Pavone <pavone@retrodev.com>
date Fri, 13 Sep 2013 19:22:46 -0700
parents 5f3344d0d42f
children f065769836e8
line wrap: on
line diff
--- a/blastem.c	Wed Sep 11 19:26:35 2013 -0700
+++ b/blastem.c	Fri Sep 13 19:22:46 2013 -0700
@@ -362,7 +362,7 @@
 			exit(1);
 		}
 		if (v_context->cycles != before_cycle) {
-			//printf("68K paused for %d (%d) cycles at cycle %d (%d)\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle);
+			printf("68K paused for %d (%d) cycles at cycle %d (%d) for write\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle);
 			context->current_cycle = v_context->cycles / MCLKS_PER_68K;
 		}
 	} else if (vdp_port < 0x18) {
@@ -402,7 +402,7 @@
 		sync_sound(gen, context->current_cycle * MCLKS_PER_Z80);
 		psg_write(gen->psg, value);
 	} else {
-		//TODO: Implement undocumented test register(s)
+		vdp_test_port_write(gen->vdp, value);
 	}
 	return context;
 }
@@ -417,6 +417,7 @@
 	uint16_t value;
 	sync_components(context, 0);
 	vdp_context * v_context = context->video_context;
+	uint32_t before_cycle = v_context->cycles;
 	if (vdp_port < 0x10) {
 		if (vdp_port < 4) {
 			value = vdp_data_port_read(v_context);
@@ -426,9 +427,15 @@
 			value = vdp_hv_counter_read(v_context);
 			//printf("HV Counter: %X at cycle %d\n", value, v_context->cycles);
 		}
+	} else if (vdp_port < 0x18){
+		printf("Illegal read from PSG  port %X\n", vdp_port);
+		exit(1);
 	} else {
-		printf("Illegal read from PSG or test register port %X\n", vdp_port);
-		exit(1);
+		value = vdp_test_port_read(v_context);
+	}
+	if (v_context->cycles != before_cycle) {
+		printf("68K paused for %d (%d) cycles at cycle %d (%d) for read\n", v_context->cycles / MCLKS_PER_68K - context->current_cycle, v_context->cycles - before_cycle, context->current_cycle, before_cycle);
+		context->current_cycle = v_context->cycles / MCLKS_PER_68K;
 	}
 	return value;
 }