Mercurial > repos > blastem
comparison backend_x86.c @ 1047:6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 27 Jul 2016 22:46:22 -0700 |
parents | 1f09994e92c5 |
children | 89cc20cf1ad3 |
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1046:a27fdf43f1a7 | 1047:6b07af1515b5 |
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1 #include "backend.h" | 1 #include "backend.h" |
2 #include "gen_x86.h" | 2 #include "gen_x86.h" |
3 | 3 |
4 void cycles(cpu_options *opts, uint32_t num) | 4 void cycles(cpu_options *opts, uint32_t num) |
5 { | 5 { |
6 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); | 6 if (opts->limit < 0) { |
7 sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); | |
8 } else { | |
9 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); | |
10 } | |
7 } | 11 } |
8 | 12 |
9 void check_cycles_int(cpu_options *opts, uint32_t address) | 13 void check_cycles_int(cpu_options *opts, uint32_t address) |
10 { | 14 { |
11 code_info *code = &opts->code; | 15 code_info *code = &opts->code; |
12 cmp_rr(code, opts->cycles, opts->limit, SZ_D); | 16 if (opts->limit < 0) { |
17 or_rr(code, opts->cycles, opts->cycles, SZ_D); | |
18 } else { | |
19 cmp_rr(code, opts->cycles, opts->limit, SZ_D); | |
20 } | |
13 code_ptr jmp_off = code->cur+1; | 21 code_ptr jmp_off = code->cur+1; |
14 jcc(code, CC_A, jmp_off+1); | 22 jcc(code, CC_NS, jmp_off+1); |
15 mov_ir(code, address, opts->scratch1, SZ_D); | 23 mov_ir(code, address, opts->scratch1, SZ_D); |
16 call(code, opts->handle_cycle_limit_int); | 24 call(code, opts->handle_cycle_limit_int); |
17 *jmp_off = code->cur - (jmp_off+1); | 25 *jmp_off = code->cur - (jmp_off+1); |
18 } | 26 } |
19 | 27 |
20 void check_cycles(cpu_options * opts) | 28 void check_cycles(cpu_options * opts) |
21 { | 29 { |
22 code_info *code = &opts->code; | 30 code_info *code = &opts->code; |
23 cmp_rr(code, opts->cycles, opts->limit, SZ_D); | 31 if (opts->limit < 0) { |
32 or_rr(code, opts->cycles, opts->cycles, SZ_D); | |
33 } else { | |
34 cmp_rr(code, opts->cycles, opts->limit, SZ_D); | |
35 } | |
24 check_alloc_code(code, MAX_INST_LEN*2); | 36 check_alloc_code(code, MAX_INST_LEN*2); |
25 code_ptr jmp_off = code->cur+1; | 37 code_ptr jmp_off = code->cur+1; |
26 jcc(code, CC_A, jmp_off+1); | 38 jcc(code, CC_NS, jmp_off+1); |
27 call(code, opts->handle_cycle_limit); | 39 call(code, opts->handle_cycle_limit); |
28 *jmp_off = code->cur - (jmp_off+1); | 40 *jmp_off = code->cur - (jmp_off+1); |
29 } | 41 } |
30 | 42 |
31 void log_address(cpu_options *opts, uint32_t address, char * format) | 43 void log_address(cpu_options *opts, uint32_t address, char * format) |