Mercurial > repos > blastem
diff backend_x86.c @ 1047:6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Wed, 27 Jul 2016 22:46:22 -0700 |
| parents | 1f09994e92c5 |
| children | 89cc20cf1ad3 |
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--- a/backend_x86.c Tue Jul 26 23:12:23 2016 -0700 +++ b/backend_x86.c Wed Jul 27 22:46:22 2016 -0700 @@ -3,15 +3,23 @@ void cycles(cpu_options *opts, uint32_t num) { - add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); + if (opts->limit < 0) { + sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); + } else { + add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); + } } void check_cycles_int(cpu_options *opts, uint32_t address) { code_info *code = &opts->code; - cmp_rr(code, opts->cycles, opts->limit, SZ_D); + if (opts->limit < 0) { + or_rr(code, opts->cycles, opts->cycles, SZ_D); + } else { + cmp_rr(code, opts->cycles, opts->limit, SZ_D); + } code_ptr jmp_off = code->cur+1; - jcc(code, CC_A, jmp_off+1); + jcc(code, CC_NS, jmp_off+1); mov_ir(code, address, opts->scratch1, SZ_D); call(code, opts->handle_cycle_limit_int); *jmp_off = code->cur - (jmp_off+1); @@ -20,10 +28,14 @@ void check_cycles(cpu_options * opts) { code_info *code = &opts->code; - cmp_rr(code, opts->cycles, opts->limit, SZ_D); + if (opts->limit < 0) { + or_rr(code, opts->cycles, opts->cycles, SZ_D); + } else { + cmp_rr(code, opts->cycles, opts->limit, SZ_D); + } check_alloc_code(code, MAX_INST_LEN*2); code_ptr jmp_off = code->cur+1; - jcc(code, CC_A, jmp_off+1); + jcc(code, CC_NS, jmp_off+1); call(code, opts->handle_cycle_limit); *jmp_off = code->cur - (jmp_off+1); }