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comparison vdp.c @ 1183:8d8c71ebbbce

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CRAM contention artifact emulation
author Michael Pavone <pavone@retrodev.com>
date Wed, 18 Jan 2017 21:30:20 -0800
parents e2b81a0f8fd8
children 9de9d2c6ebe5
comparison
equal deleted inserted replaced
1182:2a799f24563f 1183:8d8c71ebbbce
709 709
710 #define CRAM_BITS 0xEEE 710 #define CRAM_BITS 0xEEE
711 #define VSRAM_BITS 0x7FF 711 #define VSRAM_BITS 0x7FF
712 #define VSRAM_DIRTY_BITS 0xF800 712 #define VSRAM_DIRTY_BITS 0xF800
713 713
714 //rough estimate of slot number at which active display starts
715 #define BG_START_SLOT 9
716
714 void write_cram(vdp_context * context, uint16_t address, uint16_t value) 717 void write_cram(vdp_context * context, uint16_t address, uint16_t value)
715 { 718 {
716 uint16_t addr; 719 uint16_t addr;
717 if (context->regs[REG_MODE_2] & BIT_MODE_5) { 720 if (context->regs[REG_MODE_2] & BIT_MODE_5) {
718 addr = (address/2) & (CRAM_SIZE-1); 721 addr = (address/2) & (CRAM_SIZE-1);
723 context->cram[addr] = value; 726 context->cram[addr] = value;
724 context->colors[addr] = color_map[value & CRAM_BITS]; 727 context->colors[addr] = color_map[value & CRAM_BITS];
725 context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) | FBUF_SHADOW]; 728 context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) | FBUF_SHADOW];
726 context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT]; 729 context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT];
727 context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) | FBUF_MODE4]; 730 context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) | FBUF_MODE4];
731
732 if (context->hslot >= BG_START_SLOT && (
733 context->vcounter < context->inactive_start + context->border_bot
734 || context->vcounter > 0x200 - context->border_top
735 )) {
736 uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? 320/2 : 256/2;
737 if (context->hslot < bg_end_slot) {
738 uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + CRAM_SIZE*3];
739 context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color;
740 }
741 }
728 } 742 }
729 743
730 static void vdp_advance_dma(vdp_context * context) 744 static void vdp_advance_dma(vdp_context * context)
731 { 745 {
732 context->regs[REG_DMASRC_L] += 1; 746 context->regs[REG_DMASRC_L] += 1;
2104 { 2118 {
2105 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL; 2119 context->latched_mode = context->regs[REG_MODE_2] & BIT_PAL;
2106 update_video_params(context); 2120 update_video_params(context);
2107 } 2121 }
2108 2122
2109 //rough estimate of slot number at which active display starts
2110 #define BG_START_SLOT 9
2111
2112 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5) 2123 static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5)
2113 { 2124 {
2114 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest; 2125 uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest;
2115 uint8_t index_reset_value, max_draws, max_sprites; 2126 uint8_t index_reset_value, max_draws, max_sprites;
2116 uint16_t vint_line, active_line; 2127 uint16_t vint_line, active_line;
2188 } else if (context->vcounter == vint_line && context->hslot == vint_slot) { 2199 } else if (context->vcounter == vint_line && context->hslot == vint_slot) {
2189 context->flags2 |= FLAG2_VINT_PENDING; 2200 context->flags2 |= FLAG2_VINT_PENDING;
2190 context->pending_vint_start = context->cycles; 2201 context->pending_vint_start = context->cycles;
2191 } 2202 }
2192 2203
2193 if (!is_refresh(context, context->hslot)) {
2194 external_slot(context);
2195 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
2196 run_dma_src(context, context->hslot);
2197 }
2198 }
2199
2200 if (dst) { 2204 if (dst) {
2201 if (mode_5) { 2205 if (mode_5) {
2202 bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; 2206 bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F];
2203 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) { 2207 } else if (context->regs[REG_MODE_1] & BIT_MODE_4) {
2204 bg_color = context->colors[CRAM_SIZE * 3 + 0x10 + (context->regs[REG_BG_COLOR] & 0xF)]; 2208 bg_color = context->colors[CRAM_SIZE * 3 + 0x10 + (context->regs[REG_BG_COLOR] & 0xF)];
2205 } 2209 }
2206 *(dst++) = bg_color; 2210 *(dst++) = bg_color;
2207 *(dst++) = bg_color; 2211 *(dst++) = bg_color;
2208 } 2212 }
2213
2214 if (!is_refresh(context, context->hslot)) {
2215 external_slot(context);
2216 if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) {
2217 run_dma_src(context, context->hslot);
2218 }
2219 }
2220
2209 if (is_h40) { 2221 if (is_h40) {
2210 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) { 2222 if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) {
2211 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40]; 2223 context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];
2212 } else { 2224 } else {
2213 context->cycles += MCLKS_SLOT_H40; 2225 context->cycles += MCLKS_SLOT_H40;