Mercurial > repos > blastem
changeset 1183:8d8c71ebbbce
CRAM contention artifact emulation
| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Wed, 18 Jan 2017 21:30:20 -0800 |
| parents | 2a799f24563f |
| children | b1147418254a |
| files | vdp.c |
| diffstat | 1 files changed, 22 insertions(+), 10 deletions(-) [+] |
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--- a/vdp.c Wed Jan 18 07:29:06 2017 -0800 +++ b/vdp.c Wed Jan 18 21:30:20 2017 -0800 @@ -711,6 +711,9 @@ #define VSRAM_BITS 0x7FF #define VSRAM_DIRTY_BITS 0xF800 +//rough estimate of slot number at which active display starts +#define BG_START_SLOT 9 + void write_cram(vdp_context * context, uint16_t address, uint16_t value) { uint16_t addr; @@ -725,6 +728,17 @@ context->colors[addr + CRAM_SIZE] = color_map[(value & CRAM_BITS) | FBUF_SHADOW]; context->colors[addr + CRAM_SIZE*2] = color_map[(value & CRAM_BITS) | FBUF_HILIGHT]; context->colors[addr + CRAM_SIZE*3] = color_map[(value & CRAM_BITS) | FBUF_MODE4]; + + if (context->hslot >= BG_START_SLOT && ( + context->vcounter < context->inactive_start + context->border_bot + || context->vcounter > 0x200 - context->border_top + )) { + uint8_t bg_end_slot = BG_START_SLOT + (context->regs[REG_MODE_4] & BIT_H40) ? 320/2 : 256/2; + if (context->hslot < bg_end_slot) { + uint32_t color = (context->regs[REG_MODE_2] & BIT_MODE_5) ? context->colors[addr] : context->colors[addr + CRAM_SIZE*3]; + context->output[(context->hslot - BG_START_SLOT)*2 + 1] = color; + } + } } static void vdp_advance_dma(vdp_context * context) @@ -2106,9 +2120,6 @@ update_video_params(context); } -//rough estimate of slot number at which active display starts -#define BG_START_SLOT 9 - static void vdp_inactive(vdp_context *context, uint32_t target_cycles, uint8_t is_h40, uint8_t mode_5) { uint8_t buf_clear_slot, index_reset_slot, bg_end_slot, vint_slot, line_change, jump_start, jump_dest; @@ -2190,13 +2201,6 @@ context->pending_vint_start = context->cycles; } - if (!is_refresh(context, context->hslot)) { - external_slot(context); - if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) { - run_dma_src(context, context->hslot); - } - } - if (dst) { if (mode_5) { bg_color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; @@ -2206,6 +2210,14 @@ *(dst++) = bg_color; *(dst++) = bg_color; } + + if (!is_refresh(context, context->hslot)) { + external_slot(context); + if (context->flags & FLAG_DMA_RUN && !is_refresh(context, context->hslot)) { + run_dma_src(context, context->hslot); + } + } + if (is_h40) { if (context->hslot >= HSYNC_SLOT_H40 && context->hslot < HSYNC_END_H40) { context->cycles += h40_hsync_cycles[context->hslot - HSYNC_SLOT_H40];