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comparison vdp.c @ 138:aa3e1bb338c9

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Fix VDP reads
author Mike Pavone <pavone@retrodev.com>
date Mon, 31 Dec 2012 11:26:57 -0800
parents 0e7e1ccc0a81
children 576f55711d8d
comparison
equal deleted inserted replaced
137:0e7e1ccc0a81 138:aa3e1bb338c9
297 fifo_entry * start = (context->fifo_end - FIFO_SIZE); 297 fifo_entry * start = (context->fifo_end - FIFO_SIZE);
298 if (context->fifo_cur != start && start->cycle <= context->cycles) { 298 if (context->fifo_cur != start && start->cycle <= context->cycles) {
299 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { 299 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) {
300 context->flags |= FLAG_DMA_RUN; 300 context->flags |= FLAG_DMA_RUN;
301 context->dma_val = start->value; 301 context->dma_val = start->value;
302 context->address = start->address; //undo auto-increment
302 context->dma_cd = context->cd; 303 context->dma_cd = context->cd;
303 } else { 304 } else {
304 switch (context->cd & 0xF) 305 switch (start->cd & 0xF)
305 { 306 {
306 case VRAM_WRITE: 307 case VRAM_WRITE:
307 if (start->partial) { 308 if (start->partial) {
308 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); 309 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1);
309 context->vdpmem[context->address ^ 1] = start->value; 310 context->vdpmem[start->address ^ 1] = start->value;
310 } else { 311 } else {
311 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); 312 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address);
312 context->vdpmem[context->address] = start->value >> 8; 313 context->vdpmem[start->address] = start->value >> 8;
313 start->partial = 1; 314 start->partial = 1;
314 //skip auto-increment and removal of entry from fifo 315 //skip auto-increment and removal of entry from fifo
315 return; 316 return;
316 } 317 }
317 break; 318 break;
318 case CRAM_WRITE: 319 case CRAM_WRITE:
319 //printf("CRAM Write: %X to %X\n", start->value, context->address); 320 //printf("CRAM Write: %X to %X\n", start->value, context->address);
320 context->cram[(context->address/2) & (CRAM_SIZE-1)] = start->value; 321 context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value;
321 break; 322 break;
322 case VSRAM_WRITE: 323 case VSRAM_WRITE:
323 if (((context->address/2) & 63) < VSRAM_SIZE) { 324 if (((start->address/2) & 63) < VSRAM_SIZE) {
324 //printf("VSRAM Write: %X to %X\n", start->value, context->address); 325 //printf("VSRAM Write: %X to %X\n", start->value, context->address);
325 context->vsram[(context->address/2) & 63] = start->value; 326 context->vsram[(start->address/2) & 63] = start->value;
326 } 327 }
327 break; 328 break;
328 } 329 }
329 context->address += context->regs[REG_AUTOINC]; 330 //context->address += context->regs[REG_AUTOINC];
330 } 331 }
331 fifo_entry * cur = start+1; 332 fifo_entry * cur = start+1;
332 if (cur < context->fifo_cur) { 333 if (cur < context->fifo_cur) {
333 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); 334 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur));
334 } 335 }
1072 }*/ 1073 }*/
1073 while (context->fifo_cur == context->fifo_end) { 1074 while (context->fifo_cur == context->fifo_end) {
1074 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); 1075 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
1075 } 1076 }
1076 context->fifo_cur->cycle = context->cycles; 1077 context->fifo_cur->cycle = context->cycles;
1078 context->fifo_cur->address = context->address;
1077 context->fifo_cur->value = value; 1079 context->fifo_cur->value = value;
1080 context->fifo_cur->cd = context->cd;
1078 context->fifo_cur->partial = 0; 1081 context->fifo_cur->partial = 0;
1079 context->fifo_cur++; 1082 context->fifo_cur++;
1083 context->address += context->regs[REG_AUTOINC];
1080 } 1084 }
1081 1085
1082 uint16_t vdp_control_port_read(vdp_context * context) 1086 uint16_t vdp_control_port_read(vdp_context * context)
1083 { 1087 {
1084 context->flags &= ~FLAG_PENDING; 1088 context->flags &= ~FLAG_PENDING;
1101 } 1105 }
1102 1106
1103 uint16_t vdp_data_port_read(vdp_context * context) 1107 uint16_t vdp_data_port_read(vdp_context * context)
1104 { 1108 {
1105 context->flags &= ~FLAG_PENDING; 1109 context->flags &= ~FLAG_PENDING;
1106 if (!(context->cd & 1)) { 1110 if (context->cd & 1) {
1107 return 0; 1111 return 0;
1108 } 1112 }
1109 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense 1113 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense
1110 context->flags &= ~FLAG_UNUSED_SLOT; 1114 context->flags &= ~FLAG_UNUSED_SLOT;
1111 while (!(context->flags & FLAG_UNUSED_SLOT)) { 1115 while (!(context->flags & FLAG_UNUSED_SLOT)) {
1112 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); 1116 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20));
1113 } 1117 }
1114 uint16_t value = 0; 1118 uint16_t value = 0;
1115 switch (context->cd & 0x7) 1119 switch (context->cd & 0xF)
1116 { 1120 {
1117 case VRAM_READ: 1121 case VRAM_READ:
1118 value = context->vdpmem[context->address] << 8; 1122 value = context->vdpmem[context->address] << 8;
1119 context->flags &= ~FLAG_UNUSED_SLOT; 1123 context->flags &= ~FLAG_UNUSED_SLOT;
1120 while (!(context->flags & FLAG_UNUSED_SLOT)) { 1124 while (!(context->flags & FLAG_UNUSED_SLOT)) {