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comparison gentests.py @ 217:acd29e2664c6

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Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
author Mike Pavone <pavone@retrodev.com>
date Sat, 20 Apr 2013 00:29:14 -0700
parents 9126c33cc33c
children cb72780e17b1
comparison
equal deleted inserted replaced
216:0b5ec22dcda2 217:acd29e2664c6
104 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') 104 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
105 num = already.get('label', 0)+1 105 num = already.get('label', 0)+1
106 already['label'] = num 106 already['label'] = num
107 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index) 107 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
108 else: 108 else:
109 if str(self.base) in already: 109 if self.base == self.index:
110 if not valid_ram_address(already[str(self.base)]): 110 if str(self.base) in already:
111 del already[str(self.base)] 111 if not valid_ram_address(already[str(self.base)]*2):
112 self.write_init(outfile, size, already) 112 del already[str(self.base)]
113 return 113 self.write_init(outfile, size, already)
114 else: 114 return
115 base = already[str(self.base)] 115 else:
116 else: 116 base = index = already[str(self.base)]
117 base = already[str(self.base)] = random_ram_address() 117 else:
118 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n') 118 base = index = already[str(self.base)] = random_ram_address()/2
119 if str(self.index) in already: 119 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
120 index = already[str(self.index)] 120 else:
121 if self.index_size == 'w': 121 if str(self.base) in already:
122 index = index & 0xFFFF 122 if not valid_ram_address(already[str(self.base)]):
123 #sign extend index 123 del already[str(self.base)]
124 if index & 0x8000: 124 self.write_init(outfile, size, already)
125 index -= 65536 125 return
126 if not valid_ram_address(base + index): 126 else:
127 base = already[str(self.base)]
128 else:
129 base = already[str(self.base)] = random_ram_address()
130 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
131 if str(self.index) in already:
132 index = already[str(self.index)]
133 if self.index_size == 'w':
134 index = index & 0xFFFF
135 #sign extend index
136 if index & 0x8000:
137 index -= 65536
138 if not valid_ram_address(base + index):
139 index = already[str(self.index)] = randint(-64, 63)
140 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
141 else:
127 index = already[str(self.index)] = randint(-64, 63) 142 index = already[str(self.index)] = randint(-64, 63)
128 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n') 143 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
129 else:
130 index = already[str(self.index)] = randint(-64, 63)
131 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
132 address = base + index + self.disp 144 address = base + index + self.disp
133 if (address & 0xFFFFFF) < 0xE00000: 145 if (address & 0xFFFFFF) < 0xE00000:
134 if (address & 0xFFFFFF) < 128: 146 if (address & 0xFFFFFF) < 128:
135 self.disp -= (address & 0xFFFFFF) 147 self.disp -= (address & 0xFFFFFF)
136 else: 148 else:
364 return rand_immediate(size) 376 return rand_immediate(size)
365 elif mode.startswith('#(') and mode.endswith(')'): 377 elif mode.startswith('#(') and mode.endswith(')'):
366 inner = mode[2:-1] 378 inner = mode[2:-1]
367 start,sep,end = inner.partition('-') 379 start,sep,end = inner.partition('-')
368 return [Immediate(num) for num in range(int(start), int(end))] 380 return [Immediate(num) for num in range(int(start), int(end))]
381 else:
382 print "Don't know what to do with source type", mode
383 return None
369 384
370 class Inst2Op(object): 385 class Inst2Op(object):
371 def __init__(self, name, size, src, dst): 386 def __init__(self, name, size, src, dst):
372 self.name = name 387 self.name = name
373 self.size = size 388 self.size = size
385 if type(self.dst) == Register: 400 if type(self.dst) == Register:
386 del already[str(self.dst)] 401 del already[str(self.dst)]
387 402
388 def save_result(self, reg, always): 403 def save_result(self, reg, always):
389 if always or type(self.dst) != Register: 404 if always or type(self.dst) != Register:
390 return 'move.' + self.size + ' ' + str(self.dst) + ', ' + str(reg) 405 if type(self.dst) == Decrement:
406 src = Increment(self.dst.reg)
407 elif type(self.dst) == Increment:
408 src = Decrement(self.dst.reg)
409 else:
410 src = self.dst
411 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
391 else: 412 else:
392 return '' 413 return ''
393 414
394 def consume_regs(self, program): 415 def consume_regs(self, program):
395 self.src.consume_regs(program) 416 self.src.consume_regs(program)