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annotate gentests.py @ 217:acd29e2664c6

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Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
author Mike Pavone <pavone@retrodev.com>
date Sat, 20 Apr 2013 00:29:14 -0700
parents 9126c33cc33c
children cb72780e17b1
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214
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1 #!/usr/bin/env python
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2
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3 def split_fields(line):
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4 parts = []
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5 while line:
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6 field,_,line = line.partition('\t')
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7 parts.append(field.strip())
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8 while line.startswith('\t'):
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9 line = line[1:]
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10 return parts
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11
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12 class Program(object):
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13 def __init__(self, instruction):
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14 self.avail_dregs = {0,1,2,3,4,5,6,7}
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15 self.avail_aregs = {0,1,2,3,4,5,6,7}
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16 instruction.consume_regs(self)
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17 self.inst = instruction
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18
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19 def name(self):
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20 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
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21
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22 def write_rom_test(self, outfile):
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23 outfile.write('\tdc.l $0, start\n')
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24 for i in xrange(0x8, 0x100, 0x4):
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25 outfile.write('\tdc.l empty_handler\n')
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26 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\nstart:\n')
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27 outfile.write('\tmove #0, CCR\n')
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28 already = {}
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29 self.inst.write_init(outfile, already)
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30 if 'label' in already:
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31 outfile.write('lbl_' + str(already['label']) + ':\n')
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32 outfile.write('\t'+str(self.inst)+'\n')
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33 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
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34 save_ccr = self.get_dreg()
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35 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
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36 outfile.write('\tmove #$1F, CCR\n')
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37 self.inst.invalidate_dest(already)
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38 self.inst.write_init(outfile, already)
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39 if 'label' in already:
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40 outfile.write('lbl_' + str(already['label']) + ':\n')
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41 outfile.write('\t'+str(self.inst)+'\n')
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42 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
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43 outfile.write('\treset\n')
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44
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45 def consume_dreg(self, num):
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46 self.avail_dregs.discard(num)
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47
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48 def consume_areg(self, num):
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49 self.avail_aregs.discard(num)
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50
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51 def get_dreg(self):
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52 return Register('d', self.avail_dregs.pop())
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53
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54 class Register(object):
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55 def __init__(self, kind, num):
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56 self.kind = kind
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57 self.num = num
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58
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59 def __str__(self):
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60 if self.kind == 'd' or self.kind == 'a':
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61 return self.kind + str(self.num)
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62 return self.kind
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63
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64 def write_init(self, outfile, size, already):
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65 if not str(self) in already:
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66 minv,maxv = get_size_range(size)
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67 val = randint(minv,maxv)
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68 already[str(self)] = val
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69 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
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70
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71 def consume_regs(self, program):
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72 if self.kind == 'd':
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73 program.consume_dreg(self.num)
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74 elif self.kind == 'a':
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75 program.consume_areg(self.num)
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76
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77 def valid_ram_address(address, size='b'):
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78 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
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79
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80 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
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81 return randint(mina, maxa) | 0xE00000
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82
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83 class Indexed(object):
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84 def __init__(self, base, index, index_size, disp):
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85 self.base = base
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86 self.index = index
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87 self.index_size = index_size
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88 self.disp = disp
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89
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90 def write_init(self, outfile, size, already):
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91 if self.base.kind == 'pc':
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92 if str(self.index) in already:
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93 index = already[str(self.index)]
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94 if self.index_size == 'w':
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95 index = index & 0xFFFF
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96 #sign extend index
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97 if index & 0x8000:
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98 index -= 65536
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99 if index > -1024:
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100 index = already[str(self.index)] = randint(-32768, -1024)
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101 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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102 else:
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103 index = already[str(self.index)] = randint(-32768, -1024)
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104 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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105 num = already.get('label', 0)+1
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106 already['label'] = num
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107 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
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108 else:
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109 if self.base == self.index:
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110 if str(self.base) in already:
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111 if not valid_ram_address(already[str(self.base)]*2):
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112 del already[str(self.base)]
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113 self.write_init(outfile, size, already)
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114 return
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115 else:
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116 base = index = already[str(self.base)]
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117 else:
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118 base = index = already[str(self.base)] = random_ram_address()/2
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119 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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120 else:
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121 if str(self.base) in already:
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122 if not valid_ram_address(already[str(self.base)]):
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123 del already[str(self.base)]
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124 self.write_init(outfile, size, already)
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125 return
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126 else:
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127 base = already[str(self.base)]
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128 else:
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129 base = already[str(self.base)] = random_ram_address()
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130 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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131 if str(self.index) in already:
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132 index = already[str(self.index)]
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133 if self.index_size == 'w':
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134 index = index & 0xFFFF
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diff changeset
135 #sign extend index
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parents: 214
diff changeset
136 if index & 0x8000:
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137 index -= 65536
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parents: 214
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138 if not valid_ram_address(base + index):
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parents: 214
diff changeset
139 index = already[str(self.index)] = randint(-64, 63)
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parents: 214
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140 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
141 else:
214
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142 index = already[str(self.index)] = randint(-64, 63)
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143 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
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144 address = base + index + self.disp
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145 if (address & 0xFFFFFF) < 0xE00000:
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parents:
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146 if (address & 0xFFFFFF) < 128:
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147 self.disp -= (address & 0xFFFFFF)
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148 else:
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149 self.disp += 0xE00000-(address & 0xFFFFFF)
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150 address = base + index + self.disp
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151 elif (address & 0xFFFFFF) > 0xFFFFFC:
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152 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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153 address = base + index + self.disp
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154 if size != 'b' and address & 1:
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155 self.disp = self.disp ^ 1
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156 address = base + index + self.disp
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157 minv,maxv = get_size_range(size)
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158 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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159
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160 def __str__(self):
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161 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
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162
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163 def consume_regs(self, program):
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164 self.base.consume_regs(program)
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165 self.index.consume_regs(program)
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166
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167 class Displacement(object):
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168 def __init__(self, base, disp):
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169 self.base = base
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170 self.disp = disp
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171
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172 def write_init(self, outfile, size, already):
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173 if self.base.kind == 'pc':
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174 num = already.get('label', 0)+1
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175 already['label'] = num
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176 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
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parents:
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177 else:
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178 if str(self.base) in already:
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179 if not valid_ram_address(already[str(self.base)]):
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180 del already[str(self.base)]
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181 self.write_init(outfile, size, already)
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parents:
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182 return
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parents:
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183 else:
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184 base = already[str(self.base)]
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185 else:
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186 base = already[str(self.base)] = random_ram_address()
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187 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
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parents:
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188 address = base + self.disp
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parents:
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189 if (address & 0xFFFFFF) < 0xE00000:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
190 if (address & 0xFFFFFF) < 0x10000:
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parents:
diff changeset
191 self.disp -= (address & 0xFFFFFF)
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parents:
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192 else:
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193 self.disp += 0xE00000-(address & 0xFFFFFF)
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194 address = base + self.disp
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parents:
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195 elif (address & 0xFFFFFF) > 0xFFFFFC:
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196 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
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parents:
diff changeset
197 address = base + self.disp
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198 if size != 'b' and address & 1:
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199 self.disp = self.disp ^ 1
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200 address = base + self.disp
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parents:
diff changeset
201 minv,maxv = get_size_range(size)
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diff changeset
202 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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203
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parents:
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204 def __str__(self):
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parents:
diff changeset
205 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
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parents:
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206
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207 def consume_regs(self, program):
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parents:
diff changeset
208 self.base.consume_regs(program)
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parents:
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209
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diff changeset
210 class Indirect(object):
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parents:
diff changeset
211 def __init__(self, reg):
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diff changeset
212 self.reg = reg
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parents:
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213
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parents:
diff changeset
214 def __str__(self):
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parents:
diff changeset
215 return '(' + str(self.reg) + ')'
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parents:
diff changeset
216
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parents:
diff changeset
217 def write_init(self, outfile, size, already):
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parents:
diff changeset
218 if str(self.reg) in already:
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parents:
diff changeset
219 if not valid_ram_address(already[str(self.reg)], size):
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parents:
diff changeset
220 del already[str(self.reg)]
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parents:
diff changeset
221 self.write_init(outfile, size, already)
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parents:
diff changeset
222 return
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
223 else:
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parents:
diff changeset
224 address = already[str(self.reg)]
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parents:
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225 else:
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diff changeset
226 address = random_ram_address()
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parents:
diff changeset
227 if size != 'b':
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parents:
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228 address = address & 0xFFFFFFFE
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parents:
diff changeset
229 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
230 already[str(self.reg)] = address
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parents:
diff changeset
231 minv,maxv = get_size_range(size)
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parents:
diff changeset
232 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
diff changeset
233
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diff changeset
234 def consume_regs(self, program):
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parents:
diff changeset
235 self.reg.consume_regs(program)
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diff changeset
236
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diff changeset
237 class Increment(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
238 def __init__(self, reg):
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parents:
diff changeset
239 self.reg = reg
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parents:
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240
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parents:
diff changeset
241 def __str__(self):
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parents:
diff changeset
242 return '(' + str(self.reg) + ')+'
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parents:
diff changeset
243
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parents:
diff changeset
244 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
245 if str(self.reg) in already:
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parents:
diff changeset
246 if not valid_ram_address(already[str(self.reg)], size):
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parents:
diff changeset
247 del already[str(self.reg)]
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parents:
diff changeset
248 self.write_init(outfile, size, already)
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parents:
diff changeset
249 return
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parents:
diff changeset
250 else:
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parents:
diff changeset
251 address = already[str(self.reg)]
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252 else:
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253 address = random_ram_address()
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parents:
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254 if size != 'b':
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parents:
diff changeset
255 address = address & 0xFFFFFFFE
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parents:
diff changeset
256 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
257 already[str(self.reg)] = address
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parents:
diff changeset
258 minv,maxv = get_size_range(size)
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parents:
diff changeset
259 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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260
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parents:
diff changeset
261 def consume_regs(self, program):
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parents:
diff changeset
262 self.reg.consume_regs(program)
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parents:
diff changeset
263
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parents:
diff changeset
264 class Decrement(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
265 def __init__(self, reg):
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266 self.reg = reg
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parents:
diff changeset
267
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parents:
diff changeset
268 def __str__(self):
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parents:
diff changeset
269 return '-(' + str(self.reg) + ')'
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parents:
diff changeset
270
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parents:
diff changeset
271 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
272 if str(self.reg) in already:
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parents:
diff changeset
273 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
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parents:
diff changeset
274 del already[str(self.reg)]
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parents:
diff changeset
275 self.write_init(outfile, size, already)
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parents:
diff changeset
276 return
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parents:
diff changeset
277 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
278 address = already[str(self.reg)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
279 else:
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280 address = random_ram_address(mina=0xE00004)
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diff changeset
281 if size != 'b':
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282 address = address & 0xFFFFFFFE
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283 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
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parents:
diff changeset
284 already[str(self.reg)] = address
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parents:
diff changeset
285 minv,maxv = get_size_range(size)
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parents:
diff changeset
286 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
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parents:
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287
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288 def consume_regs(self, program):
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parents:
diff changeset
289 self.reg.consume_regs(program)
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parents:
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290
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parents:
diff changeset
291 class Absolute(object):
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parents:
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292 def __init__(self, address, size):
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parents:
diff changeset
293 self.address = address
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parents:
diff changeset
294 self.size = size
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parents:
diff changeset
295
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
296 def __str__(self):
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parents:
diff changeset
297 return '(' + str(self.address) + ').' + self.size
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parents:
diff changeset
298
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parents:
diff changeset
299 def write_init(self, outfile, size, already):
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parents:
diff changeset
300 minv,maxv = get_size_range(size)
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parents:
diff changeset
301 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
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parents:
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302
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parents:
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303 def consume_regs(self, program):
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parents:
diff changeset
304 pass
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parents:
diff changeset
305
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diff changeset
306 class Immediate(object):
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307 def __init__(self, value):
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parents:
diff changeset
308 self.value = value
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parents:
diff changeset
309
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
310 def __str__(self):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 return '#' + str(self.value)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
312
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
313 def write_init(self, outfile, size, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 pass
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
315
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
316 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
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317 pass
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
318
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parents:
diff changeset
319 all_dregs = [Register('d', i) for i in range(0, 8)]
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parents:
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320 all_aregs = [Register('a', i) for i in range(0, 8)]
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parents:
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321 all_indirect = [Indirect(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 all_predec = [Decrement(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 all_postinc = [Increment(reg) for reg in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 from random import randint
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
325 def all_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
326 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
327
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
328 def all_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
329 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
330
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331 def rand_pc_disp():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
333
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 def all_pc_indexed():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
335 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
336
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
337 def rand_abs_short():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
338 return [Absolute(0xFFFF8000 + randint(0, 32767), 'w') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
339
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
340 def rand_abs_long():
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
341 return [Absolute(0xFF0000 + randint(0, 65535), 'l') for x in xrange(0, 8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
343 def get_size_range(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
344 if size == 'b':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
345 return (-128, 127)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
346 elif size == 'w':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 return (-32768, 32767)
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parents:
diff changeset
348 else:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349 return (-2147483648, 2147483647)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
350
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
351 def rand_immediate(size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
352 minv,maxv = get_size_range(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
353
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
354 return [Immediate(randint(minv, maxv)) for x in xrange(0,8)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
355
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
356 def get_variations(mode, size):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
357 mapping = {
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
358 'd':all_dregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
359 'a':all_aregs,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
360 '(a)':all_indirect,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
361 '-(a)':all_predec,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
362 '(a)+':all_postinc,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
363 '(n,a)':all_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
364 '(n,a,x)':all_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
365 '(n,pc)':rand_pc_disp,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
366 '(n,pc,x)':all_pc_indexed,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
367 '(n).w':rand_abs_short,
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
368 '(n).l':rand_abs_long
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
369 }
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
370 if mode in mapping:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
371 ret = mapping[mode]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 if type(ret) != list:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
373 ret = ret()
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
374 return ret
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
375 elif mode == '#n':
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
376 return rand_immediate(size)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
377 elif mode.startswith('#(') and mode.endswith(')'):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
378 inner = mode[2:-1]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
379 start,sep,end = inner.partition('-')
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parents:
diff changeset
380 return [Immediate(num) for num in range(int(start), int(end))]
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
381 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
382 print "Don't know what to do with source type", mode
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
383 return None
214
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parents:
diff changeset
384
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
385 class Inst2Op(object):
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parents:
diff changeset
386 def __init__(self, name, size, src, dst):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
387 self.name = name
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parents:
diff changeset
388 self.size = size
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
389 self.src = src
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
390 self.dst = dst
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
391
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
392 def __str__(self):
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parents:
diff changeset
393 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
394
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
395 def write_init(self, outfile, already):
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parents:
diff changeset
396 self.src.write_init(outfile, self.size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
397 self.dst.write_init(outfile, self.size, already)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
398
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
399 def invalidate_dest(self, already):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
400 if type(self.dst) == Register:
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
401 del already[str(self.dst)]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
402
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
403 def save_result(self, reg, always):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
404 if always or type(self.dst) != Register:
217
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
405 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
406 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
407 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
408 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
409 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
Mike Pavone <pavone@retrodev.com>
parents: 214
diff changeset
410 src = self.dst
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner.
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parents: 214
diff changeset
411 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
412 else:
9126c33cc33c Add test generator, builder and runner
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
413 return ''
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
414
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
415 def consume_regs(self, program):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
416 self.src.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
417 self.dst.consume_regs(program)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
418
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
419 class Entry(object):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
420 def __init__(self, line):
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
421 fields = split_fields(line)
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
422 self.name = fields[0]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
423 sizes = fields[1]
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
424 sources = fields[2].split(';')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
425 dests = fields[3].split(';')
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Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
426 combos = []
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427 for size in sizes:
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428 for source in sources:
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429 if size != 'b' or source != 'a':
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430 for dest in dests:
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431 if size != 'b' or dest != 'a':
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432 combos.append((size, source, dest))
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433 self.cases = combos
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434
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435 def programs(self):
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436 res = []
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437 for (size, src, dst) in self.cases:
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438 sources = get_variations(src, size)
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439 dests = get_variations(dst, size)
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440 for source in sources:
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441 for dest in dests:
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442 res.append(Program(Inst2Op(self.name, size, source, dest)))
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443 return res
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444
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445 def process_entries(f):
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446 entries = []
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447 for line in f:
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448 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
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449 entries.append(Entry(line))
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450 return entries
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451
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452
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453 def main(args):
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454 entries = process_entries(open('testcases.txt'))
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455 for entry in entries:
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456 programs = entry.programs()
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457 for program in programs:
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458 f = open('generated_tests/' + program.name() + '.s68', 'w')
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459 program.write_rom_test(f)
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460 f.close()
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461
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462 if __name__ == '__main__':
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463 import sys
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464 main(sys.argv)
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465