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comparison m68k_core_x86.c @ 2620:b58ca7af1e60

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Fix nbcd in old 68K core for non-register addressing modes
author Michael Pavone <pavone@retrodev.com>
date Fri, 21 Feb 2025 23:28:07 -0800
parents d74d3998482c
children 7e86ec94c899
comparison
equal deleted inserted replaced
2619:ba2aba23b48e 2620:b58ca7af1e60
1469 } 1469 }
1470 1470
1471 void translate_m68k_abcd_sbcd(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op) 1471 void translate_m68k_abcd_sbcd(m68k_options *opts, m68kinst *inst, host_ea *src_op, host_ea *dst_op)
1472 { 1472 {
1473 code_info *code = &opts->gen.code; 1473 code_info *code = &opts->gen.code;
1474 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG && inst->dst.addr_mode != MODE_AREG_PREDEC) {
1475 //destination is in memory so we need to preserve scratch2 for the write at the end
1476 push_r(code, opts->gen.scratch2);
1477 }
1478
1474 if (inst->op == M68K_NBCD) { 1479 if (inst->op == M68K_NBCD) {
1475 if (dst_op->base != opts->gen.scratch2) { 1480 if (dst_op->base != opts->gen.scratch2) {
1476 if (dst_op->mode == MODE_REG_DIRECT) { 1481 if (dst_op->mode == MODE_REG_DIRECT) {
1477 mov_rr(code, dst_op->base, opts->gen.scratch2, SZ_B); 1482 mov_rr(code, dst_op->base, opts->gen.scratch2, SZ_B);
1478 } else { 1483 } else {
1493 mov_rr(code, dst_op->base, opts->gen.scratch1, SZ_B); 1498 mov_rr(code, dst_op->base, opts->gen.scratch1, SZ_B);
1494 } else { 1499 } else {
1495 mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch1, SZ_B); 1500 mov_rdispr(code, dst_op->base, dst_op->disp, opts->gen.scratch1, SZ_B);
1496 } 1501 }
1497 } 1502 }
1498 }
1499 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG && inst->dst.addr_mode != MODE_AREG_PREDEC) {
1500 //destination is in memory so we need to preserve scratch2 for the write at the end
1501 push_r(code, opts->gen.scratch2);
1502 } 1503 }
1503 1504
1504 //reg to reg takes 6 cycles, mem to mem is 4 cycles + all the operand fetch/writing (including 2 cycle predec penalty for first operand) 1505 //reg to reg takes 6 cycles, mem to mem is 4 cycles + all the operand fetch/writing (including 2 cycle predec penalty for first operand)
1505 cycles(&opts->gen, inst->dst.addr_mode != MODE_REG ? BUS : BUS + 2); 1506 cycles(&opts->gen, inst->dst.addr_mode != MODE_REG ? BUS : BUS + 2);
1506 uint8_t other_reg; 1507 uint8_t other_reg;