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comparison z80_to_x86.c @ 1053:b86c3ce007d9

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Implemented undocumented flag bits for rotate instructions
author Michael Pavone <pavone@retrodev.com>
date Fri, 29 Jul 2016 09:23:59 -0700
parents 366c28ac6c55
children ca38a29d2d76
comparison
equal deleted inserted replaced
1052:366c28ac6c55 1053:b86c3ce007d9
1453 src_op.mode = MODE_UNUSED; 1453 src_op.mode = MODE_UNUSED;
1454 translate_z80_reg(inst, &dst_op, opts); 1454 translate_z80_reg(inst, &dst_op, opts);
1455 } 1455 }
1456 if (dst_op.mode == MODE_REG_DIRECT) { 1456 if (dst_op.mode == MODE_REG_DIRECT) {
1457 rol_ir(code, 1, dst_op.base, SZ_B); 1457 rol_ir(code, 1, dst_op.base, SZ_B);
1458 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1458 } else { 1459 } else {
1459 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); 1460 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1461 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1462 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1460 } 1463 }
1461 if (src_op.mode == MODE_REG_DIRECT) { 1464 if (src_op.mode == MODE_REG_DIRECT) {
1462 mov_rr(code, dst_op.base, src_op.base, SZ_B); 1465 mov_rr(code, dst_op.base, src_op.base, SZ_B);
1463 } else if(src_op.mode == MODE_REG_DISPLACE8) { 1466 } else if(src_op.mode == MODE_REG_DISPLACE8) {
1464 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); 1467 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
1500 translate_z80_reg(inst, &dst_op, opts); 1503 translate_z80_reg(inst, &dst_op, opts);
1501 } 1504 }
1502 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); 1505 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1503 if (dst_op.mode == MODE_REG_DIRECT) { 1506 if (dst_op.mode == MODE_REG_DIRECT) {
1504 rcl_ir(code, 1, dst_op.base, SZ_B); 1507 rcl_ir(code, 1, dst_op.base, SZ_B);
1508 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1505 } else { 1509 } else {
1506 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); 1510 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1511 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1512 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1507 } 1513 }
1508 if (src_op.mode == MODE_REG_DIRECT) { 1514 if (src_op.mode == MODE_REG_DIRECT) {
1509 mov_rr(code, dst_op.base, src_op.base, SZ_B); 1515 mov_rr(code, dst_op.base, src_op.base, SZ_B);
1510 } else if(src_op.mode == MODE_REG_DISPLACE8) { 1516 } else if(src_op.mode == MODE_REG_DISPLACE8) {
1511 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); 1517 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
1546 src_op.mode = MODE_UNUSED; 1552 src_op.mode = MODE_UNUSED;
1547 translate_z80_reg(inst, &dst_op, opts); 1553 translate_z80_reg(inst, &dst_op, opts);
1548 } 1554 }
1549 if (dst_op.mode == MODE_REG_DIRECT) { 1555 if (dst_op.mode == MODE_REG_DIRECT) {
1550 ror_ir(code, 1, dst_op.base, SZ_B); 1556 ror_ir(code, 1, dst_op.base, SZ_B);
1557 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1551 } else { 1558 } else {
1552 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); 1559 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1560 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1561 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1553 } 1562 }
1554 if (src_op.mode == MODE_REG_DIRECT) { 1563 if (src_op.mode == MODE_REG_DIRECT) {
1555 mov_rr(code, dst_op.base, src_op.base, SZ_B); 1564 mov_rr(code, dst_op.base, src_op.base, SZ_B);
1556 } else if(src_op.mode == MODE_REG_DISPLACE8) { 1565 } else if(src_op.mode == MODE_REG_DISPLACE8) {
1557 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); 1566 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);
1593 translate_z80_reg(inst, &dst_op, opts); 1602 translate_z80_reg(inst, &dst_op, opts);
1594 } 1603 }
1595 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); 1604 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1596 if (dst_op.mode == MODE_REG_DIRECT) { 1605 if (dst_op.mode == MODE_REG_DIRECT) {
1597 rcr_ir(code, 1, dst_op.base, SZ_B); 1606 rcr_ir(code, 1, dst_op.base, SZ_B);
1607 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1598 } else { 1608 } else {
1599 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); 1609 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B);
1610 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B);
1611 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1600 } 1612 }
1601 if (src_op.mode == MODE_REG_DIRECT) { 1613 if (src_op.mode == MODE_REG_DIRECT) {
1602 mov_rr(code, dst_op.base, src_op.base, SZ_B); 1614 mov_rr(code, dst_op.base, src_op.base, SZ_B);
1603 } else if(src_op.mode == MODE_REG_DISPLACE8) { 1615 } else if(src_op.mode == MODE_REG_DISPLACE8) {
1604 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); 1616 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B);