Mercurial > repos > blastem
annotate z80_to_x86.c @ 1053:b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
author | Michael Pavone <pavone@retrodev.com> |
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date | Fri, 29 Jul 2016 09:23:59 -0700 |
parents | 366c28ac6c55 |
children | ca38a29d2d76 |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "z80inst.h" |
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7 #include "z80_to_x86.h" |
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8 #include "gen_x86.h" |
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9 #include "mem.h" |
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10 #include "util.h" |
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11 #include <stdio.h> |
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12 #include <stdlib.h> |
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13 #include <stddef.h> |
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14 #include <string.h> |
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15 |
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16 #define MODE_UNUSED (MODE_IMMED-1) |
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17 #define MAX_MCYCLE_LENGTH 6 |
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18 |
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19 //#define DO_DEBUG_PRINT |
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20 |
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21 #ifdef DO_DEBUG_PRINT |
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22 #define dprintf printf |
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23 #else |
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24 #define dprintf |
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25 #endif |
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26 |
652 | 27 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst); |
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28 void z80_handle_deferred(z80_context * context); |
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29 |
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30 uint8_t z80_size(z80inst * inst) |
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31 { |
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32 uint8_t reg = (inst->reg & 0x1F); |
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33 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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34 return reg < Z80_BC ? SZ_B : SZ_W; |
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35 } |
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36 //TODO: Handle any necessary special cases |
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37 return SZ_B; |
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38 } |
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39 |
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40 uint8_t zf_off(uint8_t flag) |
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41 { |
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42 return offsetof(z80_context, flags) + flag; |
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43 } |
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44 |
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45 uint8_t zaf_off(uint8_t flag) |
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46 { |
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47 return offsetof(z80_context, alt_flags) + flag; |
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48 } |
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49 |
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50 uint8_t zr_off(uint8_t reg) |
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51 { |
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52 if (reg > Z80_A) { |
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53 reg = z80_low_reg(reg); |
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54 } |
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55 return offsetof(z80_context, regs) + reg; |
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56 } |
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57 |
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58 uint8_t zar_off(uint8_t reg) |
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59 { |
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60 if (reg > Z80_A) { |
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61 reg = z80_low_reg(reg); |
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62 } |
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63 return offsetof(z80_context, alt_regs) + reg; |
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64 } |
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65 |
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66 void zreg_to_native(z80_options *opts, uint8_t reg, uint8_t native_reg) |
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67 { |
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68 if (opts->regs[reg] >= 0) { |
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69 mov_rr(&opts->gen.code, opts->regs[reg], native_reg, reg > Z80_A ? SZ_W : SZ_B); |
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70 } else { |
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71 mov_rdispr(&opts->gen.code, opts->gen.context_reg, zr_off(reg), native_reg, reg > Z80_A ? SZ_W : SZ_B); |
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72 } |
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73 } |
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74 |
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75 void native_to_zreg(z80_options *opts, uint8_t native_reg, uint8_t reg) |
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76 { |
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77 if (opts->regs[reg] >= 0) { |
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78 mov_rr(&opts->gen.code, native_reg, opts->regs[reg], reg > Z80_A ? SZ_W : SZ_B); |
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79 } else { |
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80 mov_rrdisp(&opts->gen.code, native_reg, opts->gen.context_reg, zr_off(reg), reg > Z80_A ? SZ_W : SZ_B); |
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81 } |
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82 } |
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83 |
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84 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts) |
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85 { |
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86 code_info *code = &opts->gen.code; |
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87 if (inst->reg == Z80_USE_IMMED) { |
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88 ea->mode = MODE_IMMED; |
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89 ea->disp = inst->immed; |
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90 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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91 ea->mode = MODE_UNUSED; |
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92 } else { |
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93 ea->mode = MODE_REG_DIRECT; |
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94 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
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95 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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96 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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97 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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98 ea->base = opts->gen.scratch1; |
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99 } else { |
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100 ea->base = opts->regs[Z80_IYL]; |
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101 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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102 } |
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103 } else if(opts->regs[inst->reg] >= 0) { |
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104 ea->base = opts->regs[inst->reg]; |
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105 if (ea->base >= AH && ea->base <= BH) { |
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106 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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107 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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108 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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109 //we can't mix an *H reg with a register that requires the REX prefix |
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110 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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111 ror_ir(code, 8, ea->base, SZ_W); |
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112 } |
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113 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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114 //temp regs require REX prefix too |
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115 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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116 ror_ir(code, 8, ea->base, SZ_W); |
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117 } |
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118 } |
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119 } else { |
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120 ea->mode = MODE_REG_DISPLACE8; |
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121 ea->base = opts->gen.context_reg; |
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122 ea->disp = zr_off(inst->reg); |
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123 } |
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124 } |
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125 } |
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126 |
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127 void z80_save_reg(z80inst * inst, z80_options * opts) |
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128 { |
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129 code_info *code = &opts->gen.code; |
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130 if (inst->reg == Z80_USE_IMMED || inst->reg == Z80_UNUSED) { |
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131 return; |
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132 } |
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133 if (inst->reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
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134 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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135 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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136 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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137 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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138 } else { |
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139 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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140 } |
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141 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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142 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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143 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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144 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
268
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145 //we can't mix an *H reg with a register that requires the REX prefix |
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146 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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147 } |
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148 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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149 //temp regs require REX prefix too |
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150 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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151 } |
213
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152 } |
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153 } |
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154 |
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155 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify) |
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156 { |
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157 code_info *code = &opts->gen.code; |
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158 uint8_t size, areg; |
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159 int8_t reg; |
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160 ea->mode = MODE_REG_DIRECT; |
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161 areg = read ? opts->gen.scratch1 : opts->gen.scratch2; |
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162 switch(inst->addr_mode & 0x1F) |
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163 { |
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164 case Z80_REG: |
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165 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
312
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166 if (inst->reg == Z80_IYL) { |
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167 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W); |
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168 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
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169 ea->base = opts->gen.scratch1; |
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170 } else { |
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171 ea->base = opts->regs[Z80_IYL]; |
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172 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
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173 } |
651
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Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
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174 } else if(opts->regs[inst->ea_reg] >= 0) { |
213
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175 ea->base = opts->regs[inst->ea_reg]; |
267
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176 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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177 uint8_t other_reg = opts->regs[inst->reg]; |
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178 #ifdef X86_64 |
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179 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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180 //we can't mix an *H reg with a register that requires the REX prefix |
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181 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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182 ror_ir(code, 8, ea->base, SZ_W); |
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183 } |
666
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184 #endif |
267
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185 } |
651
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Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
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186 } else { |
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|
187 ea->mode = MODE_REG_DISPLACE8; |
659
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Minor Z80 core cleanup
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|
188 ea->base = opts->gen.context_reg; |
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189 ea->disp = zr_off(inst->ea_reg); |
213
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190 } |
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191 break; |
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192 case Z80_REG_INDIRECT: |
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193 zreg_to_native(opts, inst->ea_reg, areg); |
213
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194 size = z80_size(inst); |
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195 if (read) { |
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196 if (modify) { |
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197 //push_r(code, opts->gen.scratch1); |
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198 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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199 } |
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200 if (size == SZ_B) { |
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|
201 call(code, opts->read_8); |
213
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|
202 } else { |
591
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|
203 call(code, opts->read_16); |
213
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|
204 } |
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|
205 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
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506
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|
206 ea->base = opts->gen.scratch1; |
213
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207 break; |
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|
208 case Z80_IMMED: |
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|
209 ea->mode = MODE_IMMED; |
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|
210 ea->disp = inst->immed; |
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|
211 break; |
4d4559b04c59
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|
212 case Z80_IMMED_INDIRECT: |
591
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213 mov_ir(code, inst->immed, areg, SZ_W); |
213
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|
214 size = z80_size(inst); |
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|
215 if (read) { |
277
765e132edd71
Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller
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216 /*if (modify) { |
591
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217 push_r(code, opts->gen.scratch1); |
277
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218 }*/ |
213
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219 if (size == SZ_B) { |
593
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220 call(code, opts->read_8); |
213
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221 } else { |
593
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222 call(code, opts->read_16); |
213
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|
223 } |
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|
224 } |
590
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WIP effort to update z80 core for code gen changes
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225 ea->base = opts->gen.scratch1; |
213
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226 break; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
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227 case Z80_IX_DISPLACE: |
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213
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228 case Z80_IY_DISPLACE: |
731
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229 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, areg); |
591
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230 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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|
231 size = z80_size(inst); |
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232 if (read) { |
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233 if (modify) { |
591
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234 //push_r(code, opts->gen.scratch1); |
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235 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
213
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|
236 } |
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|
237 if (size == SZ_B) { |
593
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|
238 call(code, opts->read_8); |
213
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|
239 } else { |
593
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|
240 call(code, opts->read_16); |
213
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|
241 } |
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|
242 } |
590
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diff
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|
243 ea->base = opts->gen.scratch1; |
213
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244 break; |
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|
245 case Z80_UNUSED: |
235
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213
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|
246 ea->mode = MODE_UNUSED; |
213
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|
247 break; |
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248 default: |
792
724bbec47f86
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249 fatal_error("Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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|
250 } |
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|
251 } |
4d4559b04c59
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|
252 |
591
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|
253 void z80_save_ea(code_info *code, z80inst * inst, z80_options * opts) |
213
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|
254 { |
267
1788e3f29c28
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266
diff
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|
255 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
731
0835cd3dfc36
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730
diff
changeset
|
256 if (inst->ea_reg == Z80_IYH && opts->regs[Z80_IYL] >= 0) { |
312
cf7ecda060c7
Properly handle instructions that use boty IYH and IYL
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311
diff
changeset
|
257 if (inst->reg == Z80_IYL) { |
591
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|
258 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
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|
259 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B); |
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changeset
|
260 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
cf7ecda060c7
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311
diff
changeset
|
261 } else { |
591
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changeset
|
262 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W); |
312
cf7ecda060c7
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311
diff
changeset
|
263 } |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
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266
diff
changeset
|
264 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
1788e3f29c28
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266
diff
changeset
|
265 uint8_t other_reg = opts->regs[inst->reg]; |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
266 #ifdef X86_64 |
269
3c054d977175
Fix IX/IY displace modes. Fix check for registers requiring REX.
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268
diff
changeset
|
267 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
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266
diff
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|
268 //we can't mix an *H reg with a register that requires the REX prefix |
591
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changeset
|
269 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
267
1788e3f29c28
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266
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|
270 } |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
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665
diff
changeset
|
271 #endif |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
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266
diff
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|
272 } |
213
4d4559b04c59
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|
273 } |
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|
274 } |
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|
275 |
593
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|
276 void z80_save_result(z80_options *opts, z80inst * inst) |
213
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|
277 { |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
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|
278 switch(inst->addr_mode & 0x1f) |
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|
279 { |
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Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
280 case Z80_REG_INDIRECT: |
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|
281 case Z80_IMMED_INDIRECT: |
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|
282 case Z80_IX_DISPLACE: |
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|
283 case Z80_IY_DISPLACE: |
1045
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Implement half-carry for INC, DEC and NEG
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|
284 if (inst->op != Z80_LD) { |
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|
285 mov_rdispr(&opts->gen.code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W); |
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|
286 } |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
287 if (z80_size(inst) == SZ_B) { |
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|
288 call(&opts->gen.code, opts->write_8); |
253
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|
289 } else { |
593
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|
290 call(&opts->gen.code, opts->write_16_lowfirst); |
253
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|
291 } |
213
4d4559b04c59
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|
292 } |
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|
293 } |
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|
294 |
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changeset
|
295 enum { |
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|
296 DONT_READ=0, |
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|
297 READ |
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|
298 }; |
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|
299 |
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
300 enum { |
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|
301 DONT_MODIFY=0, |
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|
302 MODIFY |
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303 }; |
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304 |
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305 void z80_print_regs_exit(z80_context * context) |
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306 { |
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307 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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308 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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309 context->regs[Z80_D], context->regs[Z80_E], |
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310 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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311 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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312 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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313 context->sp, context->im, context->iff1, context->iff2); |
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314 puts("--Alternate Regs--"); |
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315 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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316 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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317 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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318 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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319 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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320 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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321 exit(0); |
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322 } |
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323 |
652 | 324 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address, uint8_t interp) |
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325 { |
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326 uint32_t num_cycles; |
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327 host_ea src_op, dst_op; |
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328 uint8_t size; |
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329 z80_options *opts = context->options; |
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330 uint8_t * start = opts->gen.code.cur; |
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331 code_info *code = &opts->gen.code; |
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332 if (!interp) { |
652 | 333 check_cycles_int(&opts->gen, address); |
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334 if (context->breakpoint_flags[address / 8] & (1 << (address % 8))) { |
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335 zbreakpoint_patch(context, address, start); |
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336 } |
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337 num_cycles = 4 * inst->opcode_bytes; |
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338 add_ir(code, inst->opcode_bytes > 1 ? 2 : 1, opts->regs[Z80_R], SZ_B); |
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339 #ifdef Z80_LOG_ADDRESS |
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340 log_address(&opts->gen, address, "Z80: %X @ %d\n"); |
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341 #endif |
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342 } |
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343 switch(inst->op) |
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344 { |
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345 case Z80_LD: |
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346 size = z80_size(inst); |
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347 switch (inst->addr_mode & 0x1F) |
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348 { |
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349 case Z80_REG: |
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350 case Z80_REG_INDIRECT: |
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351 if (size != SZ_B) { |
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352 num_cycles += 2; |
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353 } |
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354 if (inst->reg == Z80_I || inst->ea_reg == Z80_I || inst->reg == Z80_R || inst->ea_reg == Z80_R) { |
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355 num_cycles += 1; |
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356 } |
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357 break; |
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358 case Z80_IMMED: |
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359 num_cycles += size == SZ_B ? 3 : 6; |
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360 break; |
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361 case Z80_IMMED_INDIRECT: |
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362 num_cycles += 6; |
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363 break; |
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364 case Z80_IX_DISPLACE: |
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365 case Z80_IY_DISPLACE: |
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366 num_cycles = 8; //3 for displacement, 5 for address addition |
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367 break; |
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368 } |
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369 cycles(&opts->gen, num_cycles); |
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370 if (inst->addr_mode & Z80_DIR) { |
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371 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY); |
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372 translate_z80_reg(inst, &src_op, opts); |
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373 } else { |
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374 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
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375 translate_z80_reg(inst, &dst_op, opts); |
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376 } |
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377 if (inst->reg == Z80_R) { |
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378 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
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379 mov_rr(code, opts->regs[Z80_A], opts->regs[Z80_R], SZ_B); |
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380 and_ir(code, 0x80, opts->gen.scratch1, SZ_B); |
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381 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zr_off(Z80_R), SZ_B); |
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382 } else if (inst->ea_reg == Z80_R && inst->addr_mode == Z80_REG) { |
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383 mov_rr(code, opts->regs[Z80_R], opts->regs[Z80_A], SZ_B); |
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384 and_ir(code, 0x7F, opts->regs[Z80_A], SZ_B); |
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385 or_rdispr(code, opts->gen.context_reg, zr_off(Z80_R), opts->regs[Z80_A], SZ_B); |
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386 } else if (src_op.mode == MODE_REG_DIRECT) { |
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387 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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388 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size); |
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389 } else { |
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390 mov_rr(code, src_op.base, dst_op.base, size); |
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391 } |
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392 } else if(src_op.mode == MODE_IMMED) { |
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393 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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394 mov_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, size); |
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395 } else { |
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396 mov_ir(code, src_op.disp, dst_op.base, size); |
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397 } |
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398 } else { |
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399 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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parents:
729
diff
changeset
|
400 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, size); |
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More bugfixes for the 32-bit build of the Z80 core
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729
diff
changeset
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401 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, size); |
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More bugfixes for the 32-bit build of the Z80 core
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729
diff
changeset
|
402 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
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parents:
729
diff
changeset
|
403 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
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parents:
729
diff
changeset
|
404 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
405 } |
842 | 406 if ((inst->ea_reg == Z80_I || inst->ea_reg == Z80_R) && inst->addr_mode == Z80_REG) { |
407 //ld a, i and ld a, r sets some flags | |
652 | 408 cmp_ir(code, 0, dst_op.base, SZ_B); |
409 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); | |
410 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); | |
821
21a69dfb6ee7
Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents:
819
diff
changeset
|
411 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);; |
652 | 412 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);; |
659
759c38bf97f8
Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents:
657
diff
changeset
|
413 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch1, SZ_B); |
652 | 414 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
415 } |
591
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Get Z80 core back into compileable state
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diff
changeset
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416 z80_save_reg(inst, opts); |
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diff
changeset
|
417 z80_save_ea(code, inst, opts); |
235
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213
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changeset
|
418 if (inst->addr_mode & Z80_DIR) { |
593
5ef3fe516da9
Z80 core is sort of working again
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parents:
592
diff
changeset
|
419 z80_save_result(opts, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
420 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
421 break; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
422 case Z80_PUSH: |
1044
1625555e346e
Properly handle redundant prefixes
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parents:
1043
diff
changeset
|
423 cycles(&opts->gen, num_cycles + 1); |
591
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424 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
235
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changeset
|
425 if (inst->reg == Z80_AF) { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
426 zreg_to_native(opts, Z80_A, opts->gen.scratch1); |
591
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|
427 shl_ir(code, 8, opts->gen.scratch1, SZ_W); |
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Partial support for undocumented flag bits
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428 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
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changeset
|
429 and_ir(code, 0x28, opts->gen.scratch1, SZ_B); |
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Partial support for undocumented flag bits
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changeset
|
430 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
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Partial support for undocumented flag bits
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changeset
|
431 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
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Partial support for undocumented flag bits
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432 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B); |
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changeset
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433 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
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changeset
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434 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B); |
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435 ror_ir(code, 2, opts->gen.scratch1, SZ_B); |
591
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436 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B); |
1049
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437 ror_ir(code, 2, opts->gen.scratch1, SZ_B); |
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438 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B); |
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parents:
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changeset
|
439 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
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changeset
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440 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B); |
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441 ror_ir(code, 1, opts->gen.scratch1, SZ_B); |
235
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Get Z80 core working for simple programs
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442 } else { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
443 zreg_to_native(opts, inst->reg, opts->gen.scratch1); |
235
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444 } |
591
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diff
changeset
|
445 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
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parents:
592
diff
changeset
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446 call(code, opts->write_16_highfirst); |
235
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447 //no call to save_z80_reg needed since there's no chance we'll use the only |
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parents:
213
diff
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|
448 //the upper half of a register pair |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
449 break; |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
450 case Z80_POP: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
451 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
452 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
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parents:
592
diff
changeset
|
453 call(code, opts->read_16); |
591
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Get Z80 core back into compileable state
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diff
changeset
|
454 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
235
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213
diff
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455 if (inst->reg == Z80_AF) { |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
456 |
591
966b46c68942
Get Z80 core back into compileable state
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diff
changeset
|
457 bt_ir(code, 0, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
458 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
459 bt_ir(code, 1, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
460 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
461 bt_ir(code, 2, opts->gen.scratch1, SZ_W); |
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Get Z80 core back into compileable state
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590
diff
changeset
|
462 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
463 bt_ir(code, 4, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
464 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
465 bt_ir(code, 6, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
466 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
467 bt_ir(code, 7, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
468 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
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parents:
1048
diff
changeset
|
469 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
470 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
471 native_to_zreg(opts, opts->gen.scratch1, Z80_A); |
235
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Get Z80 core working for simple programs
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213
diff
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|
472 } else { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
473 native_to_zreg(opts, opts->gen.scratch1, inst->reg); |
235
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474 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
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|
475 //no call to save_z80_reg needed since there's no chance we'll use the only |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
476 //the upper half of a register pair |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
477 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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239
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changeset
|
478 case Z80_EX: |
591
966b46c68942
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diff
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|
479 cycles(&opts->gen, num_cycles); |
241
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239
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480 if (inst->addr_mode == Z80_REG) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
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parents:
239
diff
changeset
|
481 if(inst->reg == Z80_AF) { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
482 zreg_to_native(opts, Z80_A, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
483 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->gen.scratch2, SZ_B); |
591
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diff
changeset
|
484 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
485 native_to_zreg(opts, opts->gen.scratch2, Z80_A); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
486 |
241
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487 //Flags are currently word aligned, so we can move |
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488 //them efficiently a word at a time |
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489 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
591
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changeset
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490 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W); |
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changeset
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491 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W); |
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changeset
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492 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W); |
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changeset
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493 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W); |
241
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494 } |
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495 } else { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
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496 if (opts->regs[Z80_DE] >= 0 && opts->regs[Z80_HL] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
716
diff
changeset
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497 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
716
diff
changeset
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498 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
716
diff
changeset
|
499 zreg_to_native(opts, Z80_DE, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
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parents:
716
diff
changeset
|
500 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
501 native_to_zreg(opts, opts->gen.scratch1, Z80_HL); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
502 native_to_zreg(opts, opts->gen.scratch2, Z80_DE); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
503 } |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
504 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
505 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
506 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
507 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
508 if (opts->regs[inst->reg] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
509 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
510 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
511 zreg_to_native(opts, inst->reg, opts->gen.scratch2); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
512 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
513 native_to_zreg(opts, opts->gen.scratch2, inst->reg); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
514 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
515 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
516 call(code, opts->write_8); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
517 cycles(&opts->gen, 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
518 uint8_t high_reg = z80_high_reg(inst->reg); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
519 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
520 add_ir(code, 1, opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
521 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
522 if (opts->regs[inst->reg] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
523 //even though some of the upper halves can be used directly |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
524 //the limitations on mixing *H regs with the REX prefix |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
525 //prevent us from taking advantage of it |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
526 uint8_t use_reg = opts->regs[inst->reg]; |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
527 ror_ir(code, 8, use_reg, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
528 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
529 //restore reg to normal rotation |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
530 ror_ir(code, 8, use_reg, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
531 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
532 zreg_to_native(opts, high_reg, opts->gen.scratch2); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
533 xchg_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
534 native_to_zreg(opts, opts->gen.scratch2, high_reg); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
535 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
536 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
537 add_ir(code, 1, opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
538 call(code, opts->write_8); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
539 cycles(&opts->gen, 2); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
540 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
541 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
542 case Z80_EXX: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
543 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
544 zreg_to_native(opts, Z80_BC, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
545 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_BC), opts->gen.scratch2, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
546 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
547 native_to_zreg(opts, opts->gen.scratch2, Z80_BC); |
840
5822c6e5642f
Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents:
828
diff
changeset
|
548 |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
549 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
550 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_HL), opts->gen.scratch2, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
551 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
552 native_to_zreg(opts, opts->gen.scratch2, Z80_HL); |
840
5822c6e5642f
Fix timing of IM instruction
Michael Pavone <pavone@retrodev.com>
parents:
828
diff
changeset
|
553 |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
554 zreg_to_native(opts, Z80_DE, opts->gen.scratch1); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
555 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_DE), opts->gen.scratch2, SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
556 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
557 native_to_zreg(opts, opts->gen.scratch2, Z80_DE); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
558 break; |
272 | 559 case Z80_LDI: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
560 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
561 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
562 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
563 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
564 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
565 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
566 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
567 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
568 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
569 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
570 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
571 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
572 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
573 cycles(&opts->gen, 2); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
574 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
575 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
576 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
577 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
578 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
579 if (opts->regs[Z80_HL] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
580 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
581 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
582 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
583 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
584 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
585 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
586 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
587 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
588 } |
821
21a69dfb6ee7
Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents:
819
diff
changeset
|
589 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
590 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
591 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
272 | 592 break; |
593 } | |
261
f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents:
259
diff
changeset
|
594 case Z80_LDIR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
595 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
596 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
597 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
598 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
599 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
600 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
601 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
602 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
603 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
604 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
605 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
606 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
607 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
608 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
609 add_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
610 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
611 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
612 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
613 if (opts->regs[Z80_HL] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
614 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
615 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
616 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
617 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
618 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
619 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
620 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
621 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
622 } |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
623 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
624 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
625 uint8_t * cont = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
626 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
627 cycles(&opts->gen, 7); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
628 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
629 jmp(code, start); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
630 *cont = code->cur - (cont + 1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
631 cycles(&opts->gen, 2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
632 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
261
f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents:
259
diff
changeset
|
633 break; |
f0c53a4bbfa3
Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write
Mike Pavone <pavone@retrodev.com>
parents:
259
diff
changeset
|
634 } |
273 | 635 case Z80_LDD: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
636 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
637 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
638 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
639 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
640 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
641 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
642 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
643 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
644 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
645 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
646 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
647 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
648 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
649 cycles(&opts->gen, 2); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
650 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
651 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
652 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
653 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
654 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
655 if (opts->regs[Z80_HL] >= 0) { |
828
22c3c52b9871
Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents:
821
diff
changeset
|
656 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
657 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
658 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
659 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
660 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
661 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
662 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
663 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
664 } |
821
21a69dfb6ee7
Implement half carry for a couple of the trivial cases
Michael Pavone <pavone@retrodev.com>
parents:
819
diff
changeset
|
665 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
666 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
667 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
273 | 668 break; |
669 } | |
670 case Z80_LDDR: { | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
671 cycles(&opts->gen, num_cycles); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
672 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
673 call(code, opts->read_8); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
674 zreg_to_native(opts, Z80_DE, opts->gen.scratch2); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
675 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
676 call(code, opts->write_8); |
1052
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
677 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_XY), opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
678 add_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
679 mov_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
680 and_ir(code, 0x8, opts->gen.scratch1, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
681 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
682 or_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
366c28ac6c55
Implement undocumented flag bits for block LD instructions
Michael Pavone <pavone@retrodev.com>
parents:
1051
diff
changeset
|
683 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
684 if (opts->regs[Z80_DE] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
685 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
686 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
687 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_DE), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
688 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
689 if (opts->regs[Z80_HL] >= 0) { |
828
22c3c52b9871
Fixed a copy pasta error in the implementation of LDD and LDDR. HL should be decremented and not incremented in those instructions.
Michael Pavone <pavone@retrodev.com>
parents:
821
diff
changeset
|
690 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
691 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
692 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
693 } |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
694 if (opts->regs[Z80_BC] >= 0) { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
695 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
696 } else { |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
697 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
698 } |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
699 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
700 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
701 uint8_t * cont = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
702 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
703 cycles(&opts->gen, 7); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
704 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
705 jmp(code, start); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
706 *cont = code->cur - (cont + 1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
707 cycles(&opts->gen, 2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
708 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
273 | 709 break; |
710 } | |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
711 case Z80_CPI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
712 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
713 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
714 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
715 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
716 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
717 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
718 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
719 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
720 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
721 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
722 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
723 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
724 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
725 if (opts->regs[Z80_HL] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
726 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
727 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
728 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
729 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
730 if (opts->regs[Z80_BC] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
731 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
732 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
733 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
734 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
735 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
736 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
737 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
738 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
739 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
740 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
741 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
742 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
743 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
744 break; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
745 case Z80_CPIR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
746 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
747 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
748 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
749 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
750 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
751 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
752 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
753 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
754 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
755 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
756 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
757 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
758 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
759 if (opts->regs[Z80_HL] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
760 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
761 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
762 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
763 } |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
764 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
765 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
766 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
767 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
768 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
769 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
770 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
parents:
1050
diff
changeset
|
771 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
772 if (opts->regs[Z80_BC] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
773 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
774 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
775 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
776 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
777 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
778 uint8_t * cont = code->cur+1; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
779 jcc(code, CC_Z, code->cur+2); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
780 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
781 uint8_t * cont2 = code->cur+1; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
782 jcc(code, CC_Z, code->cur+2); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
783 //repeat case |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
parents:
1042
diff
changeset
|
784 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
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785 jmp(code, start); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
786 *cont = code->cur - (cont + 1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
|
787 *cont2 = code->cur - (cont2 + 1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
788 break; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
789 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 case Z80_CPD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
791 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
|
792 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
793 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
794 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
795 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
796 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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797 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
798 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
799 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
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diff
changeset
|
800 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
801 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
802 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
803 cycles(&opts->gen, 5);//T-States 5 |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
804 if (opts->regs[Z80_HL] >= 0) { |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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805 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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806 } else { |
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807 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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808 } |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
809 if (opts->regs[Z80_BC] >= 0) { |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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810 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
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811 } else { |
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812 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
813 } |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
814 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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changeset
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815 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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816 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
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817 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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818 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
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Michael Pavone <pavone@retrodev.com>
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|
819 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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|
820 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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|
821 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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822 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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823 break; |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
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changeset
|
824 case Z80_CPDR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
825 cycles(&opts->gen, num_cycles);//T-States 4,4 |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
826 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
|
827 call(code, opts->read_8);//T-States 3 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
828 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
829 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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830 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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831 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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changeset
|
832 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
833 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
834 xor_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
835 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
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changeset
|
836 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1043
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
837 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
Michael Pavone <pavone@retrodev.com>
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|
838 if (opts->regs[Z80_HL] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
839 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
840 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
841 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_W); |
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Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
842 } |
1051
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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1050
diff
changeset
|
843 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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changeset
|
844 sub_rr(code, opts->gen.scratch1, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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changeset
|
845 sub_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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changeset
|
846 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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changeset
|
847 shl_ir(code, 4, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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changeset
|
848 and_irdisp(code, 0x8, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
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changeset
|
849 and_ir(code, 0x20, opts->gen.scratch2, SZ_B); |
11ff5726fd5e
Implement undocumented flag bits for block CP instructions
Michael Pavone <pavone@retrodev.com>
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changeset
|
850 or_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1043
3980ef0f6307
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|
851 if (opts->regs[Z80_BC] >= 0) { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
852 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W); |
3980ef0f6307
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|
853 } else { |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
854 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_BC), SZ_W); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
855 } |
3980ef0f6307
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|
856 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV)); |
3980ef0f6307
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|
857 uint8_t * cont = code->cur+1; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
858 jcc(code, CC_Z, code->cur+2); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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859 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
860 uint8_t * cont2 = code->cur+1; |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
861 jcc(code, CC_Z, code->cur+2); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
862 //repeat case |
3980ef0f6307
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|
863 cycles(&opts->gen, 5);//T-States 5 |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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864 jmp(code, start); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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|
865 *cont = code->cur - (cont + 1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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866 *cont2 = code->cur - (cont2 + 1); |
3980ef0f6307
Implement block CP instructions. Fix bug that would corrupt context reg in DAA. Fix flag values for when LD block instructions are interrupted part way through.
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867 break; |
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|
868 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 case Z80_ADD: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
870 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
871 num_cycles += 8; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
873 num_cycles += 3; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
875 num_cycles += 4; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
877 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
878 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
879 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
880 if (dst_op.mode == MODE_REG_DIRECT) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
881 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
882 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
883 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
884 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
885 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
886 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
887 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
888 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
889 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
890 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
891 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
892 if (dst_op.mode == MODE_REG_DIRECT) { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
893 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
894 add_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
895 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
896 add_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
897 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
898 add_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
899 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
900 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
901 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
902 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
904 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
905 add_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
906 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
907 add_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
908 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
909 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
910 add_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
911 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
912 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
913 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
915 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
916 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 if (z80_size(inst) == SZ_B) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
918 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
919 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
920 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 } |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
922 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
923 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
924 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
925 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
926 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
927 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
928 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
929 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
930 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
931 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
932 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
933 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
934 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
935 z80_save_ea(code, inst, opts); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 break; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
937 case Z80_ADC: |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
938 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
939 num_cycles += 8; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
940 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
941 num_cycles += 3; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
942 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
943 num_cycles += 4; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
944 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
945 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
946 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
947 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
948 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
949 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
950 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
951 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
952 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
953 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
954 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
955 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
956 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
957 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
958 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
959 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
960 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
961 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
962 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
963 adc_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
964 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
965 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
966 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
967 adc_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
968 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
969 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
970 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
971 } |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
972 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
973 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
974 adc_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
975 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
976 adc_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
977 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
978 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
979 adc_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
980 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
981 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
982 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
983 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
984 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
985 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
986 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
987 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
988 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
989 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
990 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
991 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
992 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
993 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
994 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
995 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
996 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
997 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
998 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
999 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1000 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1001 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1002 z80_save_ea(code, inst, opts); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1003 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 case Z80_SUB: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1005 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1006 num_cycles += 8; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1008 num_cycles += 3; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1010 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1011 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1012 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1013 if (dst_op.mode == MODE_REG_DIRECT) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1014 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1015 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1016 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1017 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1018 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1019 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1020 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1021 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1022 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1023 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1024 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1025 if (dst_op.mode == MODE_REG_DIRECT) { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1026 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1027 sub_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1028 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1029 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1030 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1031 sub_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1032 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1033 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1034 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1035 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1037 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1038 sub_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1039 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1040 sub_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1041 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1042 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1043 sub_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1044 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1045 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1046 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1048 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1049 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1050 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1051 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1052 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1053 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1054 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1055 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1056 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1057 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1058 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1059 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1060 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1061 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1062 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1063 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1064 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1065 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1066 z80_save_ea(code, inst, opts); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 break; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1068 case Z80_SBC: |
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1069 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1070 num_cycles += 8; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1071 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1072 num_cycles += 3; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1073 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1074 num_cycles += 4; |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1075 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1076 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1077 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1078 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1079 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1080 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1081 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1082 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1083 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1084 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1085 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1086 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1087 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1088 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1089 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1090 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1091 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1092 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1093 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1094 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1095 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1096 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1097 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1098 sbb_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1099 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1100 if (z80_size(inst) == SZ_B) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1101 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1102 } |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1103 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1104 if (src_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1105 sbb_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1106 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1107 sbb_irdisp(code, src_op.disp, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1108 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1109 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1110 sbb_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, z80_size(inst)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1111 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1112 mov_rdispr(code, dst_op.base, dst_op.disp + z80_size(inst) == SZ_B ? 0 : 8, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1113 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1114 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1115 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1116 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1117 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1118 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1119 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1120 if (dst_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1121 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1122 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1123 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1124 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1125 bt_ir(code, z80_size(inst) == SZ_B ? 4 : 12, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1126 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1127 if (z80_size(inst) == SZ_W & dst_op.mode == MODE_REG_DIRECT) { |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1128 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1129 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1130 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1131 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1132 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1133 z80_save_ea(code, inst, opts); |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
parents:
247
diff
changeset
|
1134 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 case Z80_AND: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1136 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1137 num_cycles += 8; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1138 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1139 num_cycles += 3; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1140 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1141 num_cycles += 4; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1142 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1143 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1144 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1145 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1146 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1147 and_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1148 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1149 and_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1150 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1151 and_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1152 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1153 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1154 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1155 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1156 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1157 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1158 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1159 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1160 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1161 z80_save_ea(code, inst, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1162 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 case Z80_OR: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1164 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1165 num_cycles += 8; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1166 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1167 num_cycles += 3; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1168 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1169 num_cycles += 4; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1170 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1171 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1172 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1173 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1174 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1175 or_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1176 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1177 or_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1178 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1179 or_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1180 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1181 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1182 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1183 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1184 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1185 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1186 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1187 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1188 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1189 z80_save_ea(code, inst, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1190 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1191 case Z80_XOR: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1192 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1193 num_cycles += 8; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1194 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1195 num_cycles += 3; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1196 } else if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1197 num_cycles += 4; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1198 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1199 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1200 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1201 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1202 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1203 xor_rr(code, src_op.base, dst_op.base, z80_size(inst)); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1204 } else if (src_op.mode == MODE_IMMED) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1205 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1206 } else { |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1207 xor_rdispr(code, src_op.base, src_op.disp, dst_op.base, z80_size(inst)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1208 } |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1209 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1210 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1211 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1212 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1213 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1214 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1215 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1216 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1217 z80_save_ea(code, inst, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1218 break; |
242 | 1219 case Z80_CP: |
1220 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1221 num_cycles += 8; |
242 | 1222 } else if(inst->addr_mode == Z80_IMMED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1223 num_cycles += 3; |
242 | 1224 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1225 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1226 translate_z80_reg(inst, &dst_op, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1227 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1228 mov_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
242 | 1229 if (src_op.mode == MODE_REG_DIRECT) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1230 sub_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1231 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1232 } else if (src_op.mode == MODE_IMMED) { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1233 sub_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1234 mov_irdisp(code, src_op.disp, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
242 | 1235 } else { |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1236 sub_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1237 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1238 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
242 | 1239 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1240 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1241 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1242 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1243 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1244 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1245 xor_rr(code, dst_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1246 if (src_op.mode == MODE_REG_DIRECT) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1247 xor_rr(code, src_op.base, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1248 } else if (src_op.mode == MODE_IMMED) { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1249 xor_ir(code, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1250 } else { |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1251 xor_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch2, z80_size(inst)); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1252 } |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1253 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1254 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1255 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1256 z80_save_ea(code, inst, opts); |
242 | 1257 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1258 case Z80_INC: |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1259 case Z80_DEC: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1260 if(z80_size(inst) == SZ_W) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1261 num_cycles += 2; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1262 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1263 cycles(&opts->gen, num_cycles); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1264 translate_z80_reg(inst, &dst_op, opts); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1265 if (dst_op.mode == MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1266 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1267 } |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1268 if (z80_size(inst) == SZ_B) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1269 if (dst_op.mode == MODE_REG_DIRECT) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1270 if (dst_op.base >= AH && dst_op.base <= BH) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1271 mov_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1272 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1273 mov_rr(code, dst_op.base, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1274 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1275 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1276 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1277 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1278 } |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1279 if (inst->op == Z80_INC) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1280 if (dst_op.mode == MODE_REG_DIRECT) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1281 add_ir(code, 1, dst_op.base, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1282 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1283 add_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1284 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1285 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1286 if (dst_op.mode == MODE_REG_DIRECT) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1287 sub_ir(code, 1, dst_op.base, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1288 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1289 sub_irdisp(code, 1, dst_op.base, dst_op.disp, z80_size(inst)); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1290 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1291 } |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1292 if (z80_size(inst) == SZ_B) { |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1293 mov_irdisp(code, inst->op == Z80_DEC, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1294 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1295 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1296 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1297 int bit = 4; |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1298 if (dst_op.mode == MODE_REG_DIRECT) { |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1299 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1300 if (dst_op.base >= AH && dst_op.base <= BH) { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1301 bit = 12; |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1302 xor_rr(code, dst_op.base - AH, opts->gen.scratch2, SZ_W); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1303 } else { |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1304 xor_rr(code, dst_op.base, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1305 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1306 } else { |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1307 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1308 xor_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch2, SZ_B); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1309 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1310 } |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1311 bt_ir(code, bit, opts->gen.scratch2, SZ_W); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1312 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1313 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1314 z80_save_reg(inst, opts); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1315 z80_save_ea(code, inst, opts); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1316 z80_save_result(opts, inst); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1317 break; |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1318 case Z80_DAA: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1319 cycles(&opts->gen, num_cycles); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1320 xor_rr(code, opts->gen.scratch2, opts->gen.scratch2, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1321 zreg_to_native(opts, Z80_A, opts->gen.scratch1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1322 and_ir(code, 0xF, opts->gen.scratch1, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1323 cmp_ir(code, 0xA, opts->gen.scratch1, SZ_B); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1324 mov_ir(code, 0xA0, opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1325 code_ptr corf_low_range = code->cur + 1; |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1326 jcc(code, CC_NC, code->cur+2); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1327 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1328 code_ptr corf_low = code->cur + 1; |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1329 jcc(code, CC_NZ, code->cur+2); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1330 code_ptr no_corf_low = code->cur + 1; |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1331 jmp(code, code->cur + 2); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1332 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1333 *corf_low_range = code->cur - (corf_low_range + 1); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1334 mov_ir(code, 0x90, opts->gen.scratch1, SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1335 *corf_low = code->cur - (corf_low + 1); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1336 mov_ir(code, 0x06, opts->gen.scratch2, SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1337 |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1338 *no_corf_low = code->cur - (no_corf_low + 1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1339 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1340 code_ptr corf_high = code->cur+1; |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1341 jcc(code, CC_NZ, code->cur+2); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1342 cmp_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1343 code_ptr no_corf_high = code->cur+1; |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1344 jcc(code, CC_C, code->cur+2); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1345 *corf_high = code->cur - (corf_high + 1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1346 or_ir(code, 0x60, opts->gen.scratch2, SZ_B); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1347 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1348 *no_corf_high = code->cur - (no_corf_high + 1); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1349 |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1350 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1351 xor_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1352 |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1353 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1354 code_ptr not_sub = code->cur+1; |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1355 jcc(code, CC_Z, code->cur+2); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1356 neg_r(code, opts->gen.scratch2, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1357 *not_sub = code->cur - (not_sub + 1); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1358 |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1359 add_rr(code, opts->gen.scratch2, opts->regs[Z80_A], SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1360 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1361 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1362 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1363 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1364 bt_ir(code, 4, opts->gen.scratch1, SZ_B); |
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1365 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1366 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1367 break; |
1046
a27fdf43f1a7
Fix DAA and implement half-carry for remaining instructions. Z80 core now passes ZEXDOC!
Michael Pavone <pavone@retrodev.com>
parents:
1045
diff
changeset
|
1368 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1369 case Z80_CPL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1370 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1371 not_r(code, opts->regs[Z80_A], SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1372 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1373 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1374 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
1375 break; |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
1376 case Z80_NEG: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1377 cycles(&opts->gen, num_cycles); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1378 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1379 neg_r(code, opts->regs[Z80_A], SZ_B); |
1049
ef7ee9919a73
Partial support for undocumented flag bits
Michael Pavone <pavone@retrodev.com>
parents:
1048
diff
changeset
|
1380 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1381 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1382 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1383 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1384 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1385 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1045
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1386 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1387 bt_ir(code, 4, opts->gen.scratch2, SZ_B); |
e0489abfdab0
Implement half-carry for INC, DEC and NEG
Michael Pavone <pavone@retrodev.com>
parents:
1044
diff
changeset
|
1388 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
274
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
1389 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1390 case Z80_CCF: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1391 cycles(&opts->gen, num_cycles); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1392 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1393 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1394 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1395 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1396 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
257 | 1397 break; |
1398 case Z80_SCF: | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1399 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1400 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1401 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1402 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
1050
d06c947a9a77
Implement undoumented flag bits for DAA, CPL, SCF and CCF
Michael Pavone <pavone@retrodev.com>
parents:
1049
diff
changeset
|
1403 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
257 | 1404 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1405 case Z80_NOP: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1406 cycles(&opts->gen, num_cycles); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1407 break; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1408 case Z80_HALT: { |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1409 code_ptr loop_top = code->cur; |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1410 //this isn't terribly efficient, but it's good enough for now |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1411 cycles(&opts->gen, num_cycles); |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1412 check_cycles_int(&opts->gen, address); |
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1413 jmp(code, loop_top); |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
1414 break; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1415 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1416 case Z80_DI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1417 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1418 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1419 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1420 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1421 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.scratch1, SZ_D); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1422 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1423 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1424 sub_rr(code, opts->gen.scratch1, opts->gen.cycles, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
1425 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1426 case Z80_EI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1427 cycles(&opts->gen, num_cycles); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1428 neg_r(code, opts->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1429 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1430 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1431 neg_r(code, opts->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
1432 add_rdispr(code, opts->gen.context_reg, offsetof(z80_context, target_cycle), opts->gen.cycles, SZ_D); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1433 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1434 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
335 | 1435 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
1436 add_irdisp(code, 4*opts->gen.clock_divider, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1437 call(code, opts->do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
1438 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1439 case Z80_IM: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1440 cycles(&opts->gen, num_cycles); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1441 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
1442 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1443 case Z80_RLC: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1444 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1445 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1446 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1447 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1448 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1449 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1450 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1451 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1452 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1453 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1454 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1455 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1456 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1457 rol_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1458 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1459 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1460 rol_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1461 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1462 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1463 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1464 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1465 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1466 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1467 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1468 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1469 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1470 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1471 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1472 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1473 //rlca does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1474 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1475 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1476 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1477 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1478 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1479 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1480 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1481 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1482 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1483 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1484 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1485 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1486 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1487 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1488 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1489 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1490 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1491 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1492 case Z80_RL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1493 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1494 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1495 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1496 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1497 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1498 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1499 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1500 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1501 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1502 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1503 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1504 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1505 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1506 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1507 rcl_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1508 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1509 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1510 rcl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1511 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1512 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1513 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1514 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1515 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1516 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1517 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1518 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1519 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1520 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1521 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1522 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1523 //rla does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1524 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1525 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1526 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1527 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1528 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1529 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1530 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1531 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1532 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1533 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1534 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1535 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1536 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1537 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1538 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1539 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1540 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1541 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1542 case Z80_RRC: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1543 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1544 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1545 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1546 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1547 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1548 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1549 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1550 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1551 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1552 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1553 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1554 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1555 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1556 ror_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1557 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1558 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1559 ror_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1560 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1561 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1562 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1563 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1564 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1565 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1566 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1567 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1568 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1569 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1570 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1571 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1572 //rrca does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1573 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1574 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1575 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1576 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1577 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1578 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1579 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1580 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1581 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1582 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1583 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1584 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1585 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1586 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1587 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1588 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1589 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1590 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1591 case Z80_RR: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1592 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1593 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1594 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1595 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1596 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1597 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1598 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1599 cycles(&opts->gen, 1); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1600 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1601 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1602 translate_z80_reg(inst, &dst_op, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1603 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1604 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1605 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1606 rcr_ir(code, 1, dst_op.base, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1607 mov_rrdisp(code, dst_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1608 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1609 rcr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
1053
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1610 mov_rdispr(code, dst_op.base, dst_op.disp, opts->gen.scratch1, SZ_B); |
b86c3ce007d9
Implemented undocumented flag bits for rotate instructions
Michael Pavone <pavone@retrodev.com>
parents:
1052
diff
changeset
|
1611 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1612 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1613 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1614 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1615 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1616 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1617 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1618 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1619 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1620 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1621 if (inst->immed) { |
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1622 //rra does not set these flags |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1623 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1624 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1625 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1626 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1627 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1628 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1629 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1630 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
651
103d5cabbe14
Fix flags for rra, rrca, rla and rlca. Fix timing for rr, rrc, rl and rlc when using IX or IY. Fix access to I and R registers (R still needs to be made 7-bit though). Fix flags for ld a, i. The fix for access to I fixes PCM playback in Titan Overdrive and music playback in Crackdown.
Michael Pavone <pavone@retrodev.com>
parents:
644
diff
changeset
|
1631 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1632 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1633 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1634 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1635 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1636 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1637 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1638 z80_save_reg(inst, opts); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1639 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1640 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1641 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1642 case Z80_SLL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1643 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1644 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1645 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1646 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1647 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1648 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1649 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1650 cycles(&opts->gen, 1); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1651 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1652 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1653 translate_z80_reg(inst, &dst_op, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1654 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1655 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1656 shl_ir(code, 1, dst_op.base, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1657 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1658 shl_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1659 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1660 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1661 if (inst->op == Z80_SLL) { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1662 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1663 or_ir(code, 1, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1664 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1665 or_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1666 } |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1667 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1668 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1669 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1670 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1671 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1672 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1673 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1674 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1675 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1676 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1677 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1678 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1679 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1680 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1681 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1682 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1683 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1684 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1685 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1686 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1687 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1688 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1689 z80_save_reg(inst, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1690 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1691 break; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1692 case Z80_SRA: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1693 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1694 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1695 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1696 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1697 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1698 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1699 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1700 cycles(&opts->gen, 1); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1701 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1702 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1703 translate_z80_reg(inst, &dst_op, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1704 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1705 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1706 sar_ir(code, 1, dst_op.base, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1707 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1708 sar_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1709 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1710 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1711 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1712 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1713 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1714 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1715 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1716 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1717 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1718 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1719 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1720 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1721 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1722 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1723 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1724 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1725 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1726 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1727 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1728 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1729 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1730 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1731 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1732 z80_save_reg(inst, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1733 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1734 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1735 case Z80_SRL: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1736 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1737 num_cycles += 8; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1738 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1739 cycles(&opts->gen, num_cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1740 if (inst->addr_mode != Z80_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1741 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1742 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1743 cycles(&opts->gen, 1); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1744 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1745 src_op.mode = MODE_UNUSED; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1746 translate_z80_reg(inst, &dst_op, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1747 } |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1748 if (dst_op.mode == MODE_REG_DIRECT) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1749 shr_ir(code, 1, dst_op.base, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1750 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1751 shr_irdisp(code, 1, dst_op.base, dst_op.disp, SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1752 } |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1753 if (src_op.mode == MODE_REG_DIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1754 mov_rr(code, dst_op.base, src_op.base, SZ_B); |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1755 } else if(src_op.mode == MODE_REG_DISPLACE8) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
1756 mov_rrdisp(code, dst_op.base, src_op.base, src_op.disp, SZ_B); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1757 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1758 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1759 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1760 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1761 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1762 cmp_ir(code, 0, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1763 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1764 cmp_irdisp(code, 0, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
1765 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1766 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1767 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1768 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1769 if (inst->addr_mode != Z80_UNUSED) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1770 z80_save_result(opts, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1771 if (src_op.mode != MODE_UNUSED) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1772 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1773 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1774 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1775 z80_save_reg(inst, opts); |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1776 } |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1777 break; |
286 | 1778 case Z80_RLD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1779 cycles(&opts->gen, num_cycles); |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1780 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1781 call(code, opts->read_8); |
286 | 1782 //Before: (HL) = 0x12, A = 0x34 |
1783 //After: (HL) = 0x24, A = 0x31 | |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1784 zreg_to_native(opts, Z80_A, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1785 shl_ir(code, 4, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1786 and_ir(code, 0xF, opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1787 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1788 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1789 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1790 //opts->gen.scratch1 = 0x0124 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1791 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1792 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1793 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1794 //set flags |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1795 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1796 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1797 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1798 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1799 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1800 |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1801 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1802 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1803 call(code, opts->write_8); |
286 | 1804 break; |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1805 case Z80_RRD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
1806 cycles(&opts->gen, num_cycles); |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1807 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1808 call(code, opts->read_8); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1809 //Before: (HL) = 0x12, A = 0x34 |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1810 //After: (HL) = 0x41, A = 0x32 |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
Michael Pavone <pavone@retrodev.com>
parents:
731
diff
changeset
|
1811 zreg_to_native(opts, Z80_A, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1812 ror_ir(code, 4, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1813 shl_ir(code, 4, opts->gen.scratch2, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1814 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1815 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B); |
967
1eb616b8cbe9
Fix bug in Z80 rrd implementation. This fixes the annoying high pitched wine in Afterburner II.
Michael Pavone <pavone@retrodev.com>
parents:
966
diff
changeset
|
1816 and_ir(code, 0xF0, opts->gen.scratch2, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1817 //opts->gen.scratch1 = 0x2001 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1818 //opts->gen.scratch2 = 0x0040 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1819 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
1820 //opts->gen.scratch1 = 0x2041 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1821 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1822 cycles(&opts->gen, 4); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1823 shr_ir(code, 4, opts->gen.scratch1, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1824 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1825 //set flags |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
1826 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1827 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1828 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1829 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
1830 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
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467
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1831 |
734
e21c274a008e
Fix RLD and RRD for the case in which HL does not map to a native register
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parents:
731
diff
changeset
|
1832 zreg_to_native(opts, Z80_HL, opts->gen.scratch2); |
591
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diff
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1833 ror_ir(code, 8, opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
1834 call(code, opts->write_8); |
287
fb840e0a48cd
Implement RRD and implement flags on RLD
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286
diff
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|
1835 break; |
308
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1836 case Z80_BIT: { |
1044
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1837 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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diff
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1838 num_cycles += 8; |
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1839 } |
591
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1840 cycles(&opts->gen, num_cycles); |
308
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1841 uint8_t bit; |
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1842 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1843 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
737
043393b79e28
Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
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diff
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1844 src_op.mode = MODE_REG_DIRECT; |
308
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1845 size = SZ_W; |
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1846 bit = inst->immed + 8; |
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1847 } else { |
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1848 size = SZ_B; |
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1849 bit = inst->immed; |
591
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1850 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY); |
308
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1851 } |
239
a5bea9711a46
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1852 if (inst->addr_mode != Z80_REG) { |
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1853 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
591
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1854 cycles(&opts->gen, 1); |
239
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1855 } |
731
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1856 if (src_op.mode == MODE_REG_DIRECT) { |
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1857 bt_ir(code, bit, src_op.base, size); |
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1858 } else { |
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1859 bt_irdisp(code, bit, src_op.base, src_op.disp, size); |
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1860 } |
591
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1861 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z)); |
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1862 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV)); |
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1863 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
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parents:
1040
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1864 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
307
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1865 if (inst->immed == 7) { |
731
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1866 if (src_op.mode == MODE_REG_DIRECT) { |
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1867 cmp_ir(code, 0, src_op.base, size); |
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1868 } else { |
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parents:
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1869 cmp_irdisp(code, 0, src_op.base, src_op.disp, size); |
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1870 } |
591
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1871 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
307
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1872 } else { |
591
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1873 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
307
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1874 } |
1049
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1875 |
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1876 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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1877 if (src_op.mode == MODE_REG_DIRECT) { |
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1878 if (size == SZ_W) { |
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1879 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W); |
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1880 shr_ir(code, 8, opts->gen.scratch1, SZ_W); |
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1881 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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1882 } else { |
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1883 mov_rrdisp(code, src_op.base, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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1884 } |
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1885 } else { |
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1886 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
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1887 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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1888 } |
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1889 } else if((inst->addr_mode & 0x1F) != Z80_REG_INDIRECT) { |
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1890 zreg_to_native(opts, (inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY, opts->gen.scratch2); |
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1891 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, opts->gen.scratch2, SZ_W); |
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1892 shr_ir(code, 8, opts->gen.scratch2, SZ_W); |
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1893 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(ZF_XY), SZ_B); |
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1894 } |
239
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1895 break; |
308
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1896 } |
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1897 case Z80_SET: { |
1044
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1898 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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1899 num_cycles += 8; |
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1900 } |
591
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1901 cycles(&opts->gen, num_cycles); |
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1902 uint8_t bit; |
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1903 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1904 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
737
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Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
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1905 src_op.mode = MODE_REG_DIRECT; |
308
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1906 size = SZ_W; |
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1907 bit = inst->immed + 8; |
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1908 } else { |
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1909 size = SZ_B; |
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1910 bit = inst->immed; |
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1911 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
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1912 } |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
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1913 if (inst->reg != Z80_USE_IMMED) { |
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1914 translate_z80_reg(inst, &dst_op, opts); |
299
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1915 } |
247
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1916 if (inst->addr_mode != Z80_REG) { |
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1917 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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1918 cycles(&opts->gen, 1); |
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1919 } |
731
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1920 if (src_op.mode == MODE_REG_DIRECT) { |
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1921 bts_ir(code, bit, src_op.base, size); |
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1922 } else { |
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1923 bts_irdisp(code, bit, src_op.base, src_op.disp, size); |
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1924 } |
299
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1925 if (inst->reg != Z80_USE_IMMED) { |
308
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1926 if (size == SZ_W) { |
666
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In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
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1927 #ifdef X86_64 |
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1928 if (dst_op.base >= R8) { |
591
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diff
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1929 ror_ir(code, 8, src_op.base, SZ_W); |
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1930 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
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1931 ror_ir(code, 8, src_op.base, SZ_W); |
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1932 } else { |
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1933 #endif |
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1934 if (dst_op.mode == MODE_REG_DIRECT) { |
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1935 zreg_to_native(opts, inst->ea_reg, dst_op.base); |
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1936 } else { |
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|
1937 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1); |
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1938 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
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1939 } |
666
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In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
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parents:
665
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|
1940 #ifdef X86_64 |
505
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The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
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parents:
467
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|
1941 } |
666
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|
1942 #endif |
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1943 } else { |
731
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1944 if (dst_op.mode == MODE_REG_DIRECT) { |
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1945 if (src_op.mode == MODE_REG_DIRECT) { |
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1946 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
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1947 } else { |
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1948 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B); |
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1949 } |
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1950 } else if (src_op.mode == MODE_REG_DIRECT) { |
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1951 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B); |
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1952 } else { |
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1953 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
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1954 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
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1955 } |
308
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1956 } |
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1957 } |
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1958 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
593
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1959 z80_save_result(opts, inst); |
308
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1960 if (inst->reg != Z80_USE_IMMED) { |
591
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1961 z80_save_reg(inst, opts); |
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1962 } |
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1963 } |
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1964 break; |
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1965 } |
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1966 case Z80_RES: { |
1044
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1967 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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1968 num_cycles += 8; |
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1969 } |
591
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1970 cycles(&opts->gen, num_cycles); |
308
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1971 uint8_t bit; |
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1972 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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1973 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
737
043393b79e28
Fixes for the 32-bit build accidentally introduced a bug into the 64-bit build, this commit fixes the regression
Michael Pavone <pavone@retrodev.com>
parents:
735
diff
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|
1974 src_op.mode = MODE_REG_DIRECT; |
308
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1975 size = SZ_W; |
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diff
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|
1976 bit = inst->immed + 8; |
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307
diff
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|
1977 } else { |
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307
diff
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|
1978 size = SZ_B; |
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parents:
307
diff
changeset
|
1979 bit = inst->immed; |
591
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parents:
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|
1980 translate_z80_ea(inst, &src_op, opts, READ, MODIFY); |
308
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diff
changeset
|
1981 } |
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changeset
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1982 if (inst->reg != Z80_USE_IMMED) { |
591
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parents:
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diff
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|
1983 translate_z80_reg(inst, &dst_op, opts); |
308
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parents:
307
diff
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|
1984 } |
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diff
changeset
|
1985 if (inst->addr_mode != Z80_REG) { |
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
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diff
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|
1986 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
591
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parents:
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diff
changeset
|
1987 cycles(&opts->gen, 1); |
308
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parents:
307
diff
changeset
|
1988 } |
731
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parents:
730
diff
changeset
|
1989 if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
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parents:
730
diff
changeset
|
1990 btr_ir(code, bit, src_op.base, size); |
0835cd3dfc36
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parents:
730
diff
changeset
|
1991 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
1992 btr_irdisp(code, bit, src_op.base, src_op.disp, size); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
1993 } |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1994 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1995 if (size == SZ_W) { |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
1996 #ifdef X86_64 |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
1997 if (dst_op.base >= R8) { |
591
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Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1998 ror_ir(code, 8, src_op.base, SZ_W); |
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Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
1999 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
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parents:
590
diff
changeset
|
2000 ror_ir(code, 8, src_op.base, SZ_W); |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
2001 } else { |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2002 #endif |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
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parents:
730
diff
changeset
|
2003 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2004 zreg_to_native(opts, inst->ea_reg, dst_op.base); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2005 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2006 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2007 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2008 } |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2009 #ifdef X86_64 |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2010 } |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2011 #endif |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
2012 } else { |
731
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2013 if (dst_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2014 if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2015 mov_rr(code, src_op.base, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2016 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2017 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2018 } |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2019 } else if (src_op.mode == MODE_REG_DIRECT) { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2020 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2021 } else { |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2022 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2023 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
0835cd3dfc36
Z80 test cases that passed on 64-bit now pass on 32-bit
Michael Pavone <pavone@retrodev.com>
parents:
730
diff
changeset
|
2024 } |
308
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Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
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parents:
307
diff
changeset
|
2025 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
2026 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
2027 if (inst->addr_mode != Z80_REG) { |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2028 z80_save_result(opts, inst); |
299
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Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
2029 if (inst->reg != Z80_USE_IMMED) { |
591
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Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2030 z80_save_reg(inst, opts); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
2031 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
2032 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
2033 break; |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
2034 } |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2035 case Z80_JP: { |
506
a3b48a57e847
Fix timing of certain ld and jp instructions in the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
505
diff
changeset
|
2036 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2037 num_cycles += 6; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2038 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2039 cycles(&opts->gen, num_cycles); |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2040 if (inst->addr_mode != Z80_REG_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2041 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2042 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2043 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2044 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2045 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2046 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2047 jmp(code, call_dst); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2048 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2049 if (inst->addr_mode == Z80_REG_INDIRECT) { |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
2050 zreg_to_native(opts, inst->ea_reg, opts->gen.scratch1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2051 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2052 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2053 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2054 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2055 jmp_r(code, opts->gen.scratch1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2056 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2057 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2058 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2059 case Z80_JPCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2060 cycles(&opts->gen, num_cycles + 3);//T States: 4,3 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2061 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2062 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2063 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2064 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2065 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2066 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2067 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2068 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2069 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2070 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2071 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2072 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2073 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2074 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2075 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2076 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2077 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2078 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2079 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
2080 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2081 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2082 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2083 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2084 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2085 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2086 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2087 cycles(&opts->gen, 5);//T States: 5 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2088 uint16_t dest_addr = inst->immed; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2089 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2090 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2091 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2092 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2093 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2094 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2095 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2096 *no_jump_off = code->cur - (no_jump_off+1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2097 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2098 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2099 case Z80_JR: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2100 cycles(&opts->gen, num_cycles + 8);//T States: 4,3,5 |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2101 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2102 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2103 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2104 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2105 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2106 call_dst = code->cur + 256; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2107 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2108 jmp(code, call_dst); |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2109 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
2110 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2111 case Z80_JRCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2112 cycles(&opts->gen, num_cycles + 3);//T States: 4,3 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2113 uint8_t cond = CC_Z; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2114 switch (inst->reg) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2115 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2116 case Z80_CC_NZ: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2117 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2118 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2119 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2120 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2121 case Z80_CC_NC: |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2122 cond = CC_NZ; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2123 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2124 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2125 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2126 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2127 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2128 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2129 cycles(&opts->gen, 5);//T States: 5 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2130 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2131 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2132 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2133 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2134 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2135 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2136 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2137 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2138 *no_jump_off = code->cur - (no_jump_off+1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2139 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2140 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2141 case Z80_DJNZ: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2142 cycles(&opts->gen, num_cycles + 4);//T States: 5,3 |
730
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2143 if (opts->regs[Z80_B] >= 0) { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2144 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2145 } else { |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2146 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
38e9bee03749
More bugfixes for the 32-bit build of the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
729
diff
changeset
|
2147 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2148 uint8_t *no_jump_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2149 jcc(code, CC_Z, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2150 cycles(&opts->gen, 5);//T States: 5 |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2151 uint16_t dest_addr = address + inst->immed + 2; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2152 code_ptr call_dst = z80_get_native_address(context, dest_addr); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2153 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2154 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2155 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2156 call_dst = code->cur + 256; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2157 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2158 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2159 *no_jump_off = code->cur - (no_jump_off+1); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2160 break; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2161 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2162 case Z80_CALL: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2163 cycles(&opts->gen, num_cycles + 7);//T States: 4,3,4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2164 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2165 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2166 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2167 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2168 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2169 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2170 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2171 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2172 call_dst = code->cur + 256; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2173 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2174 jmp(code, call_dst); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2175 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2176 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2177 case Z80_CALLCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2178 cycles(&opts->gen, num_cycles + 6);//T States: 4,3,3 (false case) |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2179 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2180 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2181 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2182 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2183 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2184 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2185 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2186 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2187 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2188 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2189 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2190 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2191 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2192 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2193 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2194 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2195 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2196 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2197 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
2198 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2199 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2200 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2201 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2202 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2203 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2204 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2205 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2206 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2207 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2208 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2209 call(code, opts->write_16_highfirst);//T States: 3, 3 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2210 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2211 if (!call_dst) { |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2212 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2213 //fake address to force large displacement |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2214 call_dst = code->cur + 256; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2215 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2216 jmp(code, call_dst); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2217 *no_call_off = code->cur - (no_call_off+1); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
2218 break; |
682 | 2219 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2220 case Z80_RET: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2221 cycles(&opts->gen, num_cycles);//T States: 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2222 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2223 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2224 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2225 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2226 jmp_r(code, opts->gen.scratch1); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2227 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2228 case Z80_RETCC: { |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2229 cycles(&opts->gen, num_cycles + 1);//T States: 5 |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2230 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2231 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2232 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2233 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2234 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2235 case Z80_CC_Z: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2236 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2237 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2238 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2239 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2240 case Z80_CC_C: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2241 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2242 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2243 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2244 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2245 case Z80_CC_PE: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2246 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2247 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2248 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
2249 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2250 case Z80_CC_M: |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2251 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2252 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2253 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2254 uint8_t *no_call_off = code->cur+1; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2255 jcc(code, cond, code->cur+2); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2256 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2257 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2258 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2259 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2260 jmp_r(code, opts->gen.scratch1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2261 *no_call_off = code->cur - (no_call_off+1); |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2262 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
2263 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2264 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2265 //For some systems, this may need a callback for signalling interrupt routine completion |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2266 cycles(&opts->gen, num_cycles);//T States: 4, 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2267 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2268 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2269 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2270 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2271 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2272 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2273 case Z80_RETN: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2274 cycles(&opts->gen, num_cycles);//T States: 4, 4 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2275 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2276 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2277 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2278 call(code, opts->read_16);//T STates: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2279 add_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2280 call(code, opts->native_addr); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2281 jmp_r(code, opts->gen.scratch1); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2282 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2283 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2284 //RST is basically CALL to an address in page 0 |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2285 cycles(&opts->gen, num_cycles + 1);//T States: 5 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2286 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2287 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2288 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2289 call(code, opts->write_16_highfirst);//T States: 3, 3 |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2290 code_ptr call_dst = z80_get_native_address(context, inst->immed); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2291 if (!call_dst) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2292 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2293 //fake address to force large displacement |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2294 call_dst = code->cur + 256; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2295 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2296 jmp(code, call_dst); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2297 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
2298 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2299 case Z80_IN: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2300 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2301 num_cycles += 3; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2302 } |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2303 cycles(&opts->gen, num_cycles);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2304 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2305 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2306 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2307 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2308 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2309 call(code, opts->read_io); |
1042
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2310 if (inst->addr_mode != Z80_IMMED_INDIRECT) { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2311 or_rr(code, opts->gen.scratch1, opts->gen.scratch1, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2312 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2313 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2314 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2315 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2316 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2317 } |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2318 if (inst->reg != Z80_UNUSED) { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2319 translate_z80_reg(inst, &dst_op, opts); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2320 if (dst_op.mode == MODE_REG_DIRECT) { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2321 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2322 } else { |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2323 mov_rrdisp(code, opts->gen.scratch1, dst_op.base, dst_op.disp, SZ_B); |
a6c6b621d0dc
Implement Z80 DAA. Implement half-carry flag for the rest of the "easy" cases. Implement flags for IN instruction. Fix implementation of IN for IN F, (C) case
Michael Pavone <pavone@retrodev.com>
parents:
1040
diff
changeset
|
2324 } |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2325 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2326 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2327 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2328 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2329 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2330 case Z80_IND: |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2331 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2332 case Z80_OUT: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2333 if (inst->reg == Z80_A) { |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2334 num_cycles += 3; |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2335 } |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2336 cycles(&opts->gen, num_cycles);//T States: 4 3/4 |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2337 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2338 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2339 } else { |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2340 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2341 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2342 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2343 translate_z80_reg(inst, &src_op, opts); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2344 if (src_op.mode == MODE_REG_DIRECT) { |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2345 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2346 } else if (src_op.mode == MODE_IMMED) { |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2347 mov_ir(code, src_op.disp, opts->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2348 } else { |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2349 mov_rdispr(code, src_op.base, src_op.disp, opts->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
2350 } |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2351 call(code, opts->write_io); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2352 z80_save_reg(inst, opts); |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
2353 break; |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2354 case Z80_OUTI: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2355 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2356 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2357 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2358 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2359 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2360 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2361 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2362 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2363 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2364 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2365 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2366 //increment HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2367 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2368 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2369 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2370 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2371 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2372 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2373 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2374 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2375 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2376 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2377 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2378 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2379 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2380 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2381 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2382 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2383 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2384 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2385 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2386 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2387 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2388 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2389 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2390 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2391 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2392 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2393 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2394 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2395 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2396 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2397 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2398 case Z80_OTIR: { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2399 code_ptr start = code->cur; |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2400 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2401 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2402 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2403 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2404 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2405 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2406 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2407 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2408 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2409 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2410 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2411 //increment HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2412 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2413 add_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2414 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2415 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2416 add_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2417 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2418 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2419 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2420 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2421 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2422 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2423 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2424 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2425 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2426 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2427 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2428 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2429 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2430 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2431 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2432 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2433 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2434 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2435 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2436 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2437 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2438 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2439 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2440 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2441 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2442 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2443 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2444 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2445 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2446 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2447 code_ptr done = code->cur+1; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2448 jcc(code, CC_Z, code->cur+2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2449 cycles(&opts->gen, 5); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2450 jmp(code, start); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2451 *done = code->cur - (done + 1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2452 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2453 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2454 case Z80_OUTD: |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2455 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2456 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2457 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2458 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2459 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2460 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2461 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2462 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2463 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2464 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2465 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2466 //decrement HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2467 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2468 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2469 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2470 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2471 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2472 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2473 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2474 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2475 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2476 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2477 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2478 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2479 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2480 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2481 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2482 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2483 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2484 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2485 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2486 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2487 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2488 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2489 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2490 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2491 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2492 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2493 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2494 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2495 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2496 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2497 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2498 case Z80_OTDR: { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2499 code_ptr start = code->cur; |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2500 cycles(&opts->gen, num_cycles + 1);//T States: 4, 5 |
1040
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2501 //read from (HL) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2502 zreg_to_native(opts, Z80_HL, opts->gen.scratch1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2503 call(code, opts->read_8);//T states 3 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2504 //undocumented N flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2505 //flag set on bit 7 of value written |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2506 bt_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2507 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_N)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2508 //write to IO (C) |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2509 zreg_to_native(opts, Z80_C, opts->gen.scratch2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2510 call(code, opts->write_io);//T states 4 |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2511 //increment HL |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2512 if (opts->regs[Z80_HL] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2513 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2514 add_rr(code, opts->regs[Z80_L], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2515 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2516 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_HL), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2517 add_rdispr(code, opts->gen.context_reg, zr_off(Z80_L), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2518 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2519 //undocumented C and H flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2520 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2521 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2522 //decrement B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2523 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2524 sub_ir(code, 1, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2525 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2526 sub_irdisp(code, 1, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2527 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2528 //undocumented Z and S flag behavior, set based on decrement of B |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2529 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2530 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2531 //crazy undocumented P/V flag behavior |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2532 and_ir(code, 7, opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2533 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2534 //deal with silly x86-64 restrictions on *H registers |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2535 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2536 xor_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2537 ror_ir(code, 8, opts->regs[Z80_BC], SZ_W); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2538 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2539 xor_rdispr(code, opts->gen.context_reg, zr_off(Z80_B), opts->gen.scratch1, SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2540 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2541 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2542 if (opts->regs[Z80_B] >= 0) { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2543 cmp_ir(code, 0, opts->regs[Z80_B], SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2544 } else { |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2545 cmp_irdisp(code, 0, opts->gen.context_reg, zr_off(Z80_B), SZ_B); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2546 } |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2547 code_ptr done = code->cur+1; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2548 jcc(code, CC_Z, code->cur+2); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2549 cycles(&opts->gen, 5); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2550 jmp(code, start); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2551 *done = code->cur - (done + 1); |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2552 break; |
fbfb821e92a8
Implement Z80 block OUT instructions. Fixes Power Monger
Michael Pavone <pavone@retrodev.com>
parents:
967
diff
changeset
|
2553 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2554 default: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2555 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
2556 z80_disasm(inst, disbuf, address); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
2557 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
2558 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
2559 fclose(f); |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2560 fatal_error("unimplemented Z80 instruction: %s at %X\nZ80 RAM has been saved to zram.bin for debugging", disbuf, address); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2561 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2562 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2563 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2564 |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2565 uint8_t * z80_interp_handler(uint8_t opcode, z80_context * context) |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2566 { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2567 if (!context->interp_code[opcode]) { |
755
7306b3967c51
Cleanup some warnings under clang through a combination of code fixes and supressing specific warnings
Michael Pavone <pavone@retrodev.com>
parents:
737
diff
changeset
|
2568 if (opcode == 0xCB || (opcode >= 0xDD && (opcode & 0xF) == 0xD)) { |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2569 fatal_error("Encountered prefix byte %X at address %X. Z80 interpeter doesn't support those yet.", opcode, context->pc); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2570 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2571 uint8_t codebuf[8]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2572 memset(codebuf, 0, sizeof(codebuf)); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2573 codebuf[0] = opcode; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2574 z80inst inst; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2575 uint8_t * after = z80_decode(codebuf, &inst); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2576 if (after - codebuf > 1) { |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2577 fatal_error("Encountered multi-byte Z80 instruction at %X. Z80 interpeter doesn't support those yet.", context->pc); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2578 } |
652 | 2579 |
2580 z80_options * opts = context->options; | |
2581 code_info *code = &opts->gen.code; | |
2582 check_alloc_code(code, ZMAX_NATIVE_SIZE); | |
2583 context->interp_code[opcode] = code->cur; | |
2584 translate_z80inst(&inst, context, 0, 1); | |
2585 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, pc), opts->gen.scratch1, SZ_W); | |
2586 add_ir(code, after - codebuf, opts->gen.scratch1, SZ_W); | |
2587 call(code, opts->native_addr); | |
2588 jmp_r(code, opts->gen.scratch1); | |
715
1c2020d3e275
Call z80_handle_deferred after generating an insruction handler so that instructions like rst work correctly
Michael Pavone <pavone@retrodev.com>
parents:
712
diff
changeset
|
2589 z80_handle_deferred(context); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2590 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2591 return context->interp_code[opcode]; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2592 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2593 |
652 | 2594 code_info z80_make_interp_stub(z80_context * context, uint16_t address) |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2595 { |
652 | 2596 z80_options *opts = context->options; |
2597 code_info * code = &opts->gen.code; | |
2598 check_alloc_code(code, 32); | |
2599 code_info stub = {code->cur, NULL}; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2600 //TODO: make this play well with the breakpoint code |
652 | 2601 mov_ir(code, address, opts->gen.scratch1, SZ_W); |
2602 call(code, opts->read_8); | |
1044
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2603 //opcode fetch M-cycles have one extra T-state |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2604 cycles(&opts->gen, 1); |
1625555e346e
Properly handle redundant prefixes
Michael Pavone <pavone@retrodev.com>
parents:
1043
diff
changeset
|
2605 //TODO: increment R |
652 | 2606 check_cycles_int(&opts->gen, address); |
2607 call(code, opts->gen.save_context); | |
2608 mov_irdisp(code, address, opts->gen.context_reg, offsetof(z80_context, pc), SZ_W); | |
2609 push_r(code, opts->gen.context_reg); | |
712
382a2b5b70c0
Fix crash bug in Z80 interpreter
Michael Pavone <pavone@retrodev.com>
parents:
702
diff
changeset
|
2610 call_args(code, (code_ptr)z80_interp_handler, 2, opts->gen.scratch1, opts->gen.context_reg); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
2611 mov_rr(code, RAX, opts->gen.scratch1, SZ_PTR); |
652 | 2612 pop_r(code, opts->gen.context_reg); |
2613 call(code, opts->gen.load_context); | |
2614 jmp_r(code, opts->gen.scratch1); | |
2615 stub.last = code->cur; | |
2616 return stub; | |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2617 } |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2618 |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2619 |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2620 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2621 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2622 native_map_slot *map; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2623 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2624 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2625 map = context->static_code_map; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2626 } else { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2627 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2628 map = context->banked_code_map; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2629 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2630 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
2631 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2632 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2633 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
2634 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2635 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2636 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2637 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2638 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2639 { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2640 //TODO: Fix for addresses >= 0x4000 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2641 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2642 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2643 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2644 return opts->gen.ram_inst_sizes[0][address & 0x1FFF]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2645 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2646 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2647 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2648 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2649 uint32_t orig_address = address; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2650 native_map_slot *map; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2651 z80_options * opts = context->options; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2652 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2653 address &= 0x1FFF; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2654 map = context->static_code_map; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2655 opts->gen.ram_inst_sizes[0][address] = native_size; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2656 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2657 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2658 } else { |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2659 //HERE |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2660 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2661 map = context->banked_code_map; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2662 if (!map->offsets) { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2663 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2664 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2665 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2666 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2667 if (!map->base) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2668 map->base = native_address; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2669 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2670 map->offsets[address] = native_address - map->base; |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
2671 for(--size, orig_address++; size; --size, orig_address++) { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2672 address = orig_address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2673 if (address < 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2674 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2675 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2676 } else { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2677 address -= 0x4000; |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2678 map = context->banked_code_map; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2679 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2680 if (!map->offsets) { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2681 map->offsets = malloc(sizeof(int32_t) * 0xC000); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2682 memset(map->offsets, 0xFF, sizeof(int32_t) * 0xC000); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2683 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2684 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2685 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2686 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2687 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2688 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2689 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2690 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2691 { |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2692 //TODO: Fixme for address >= 0x4000 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2693 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2694 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2695 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2696 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2697 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2698 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2699 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2700 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2701 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2702 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2703 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2704 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2705 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2706 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2707 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2708 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2709 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2710 if (inst_start != INVALID_INSTRUCTION_START) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2711 code_ptr dst = z80_get_native_address(context, inst_start); |
899
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
2712 code_info code = {dst, dst+32, 0}; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2713 z80_options * opts = context->options; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
2714 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code.cur, inst_start, address); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2715 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2716 call(&code, opts->retrans_stub); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2717 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2718 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2719 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2720 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2721 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2722 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2723 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2724 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2725 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2726 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2727 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2728 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2729 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2730 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2731 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2732 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2733 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2734 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2735 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2736 z80_options * opts = context->options; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2737 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2738 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2739 translate_z80_stream(context, opts->gen.deferred->address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2740 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2741 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2742 |
559
6b248602ab84
blastem builds and almost works on OS X now
Mike Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2743 extern void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) asm("z80_retranslate_inst"); |
390
561fe3ea3fc8
Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word
Mike Pavone <pavone@retrodev.com>
parents:
389
diff
changeset
|
2744 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start) |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2745 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2746 char disbuf[80]; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2747 z80_options * opts = context->options; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2748 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2749 code_info *code = &opts->gen.code; |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2750 uint8_t *after, *inst = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2751 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2752 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2753 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2754 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
2755 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2756 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2757 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2758 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2759 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
2760 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2761 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2762 if (orig_size != ZMAX_NATIVE_SIZE) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
2763 check_alloc_code(code, ZMAX_NATIVE_SIZE); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2764 code_ptr start = code->cur; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2765 deferred_addr * orig_deferred = opts->gen.deferred; |
652 | 2766 translate_z80inst(&instbuf, context, address, 0); |
644
2d7e84ae818c
Temporarily comment out code to translate Z80 instructions in place as in rare cases it can stomp the next instruction if a branch goes from a short from to a long one
Michael Pavone <pavone@retrodev.com>
parents:
628
diff
changeset
|
2767 /* |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2768 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2769 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2770 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2771 remove_deferred_until(&opts->gen.deferred, orig_deferred); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2772 native_end = translate_z80inst(&instbuf, orig_start, context, address, 0); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2773 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2774 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2775 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2776 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2777 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2778 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2779 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2780 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2781 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2782 } |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2783 }*/ |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2784 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2785 code_info tmp_code = {orig_start, orig_start + 16}; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2786 jmp(&tmp_code, start); |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
2787 tmp_code = *code; |
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
2788 code->cur = start + ZMAX_NATIVE_SIZE; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2789 if (!z80_is_terminal(&instbuf)) { |
597
8d6ae5b3b87b
Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place
Michael Pavone <pavone@retrodev.com>
parents:
594
diff
changeset
|
2790 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst)); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
2791 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2792 z80_handle_deferred(context); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2793 return start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2794 } else { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2795 code_info tmp_code = *code; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2796 code->cur = orig_start; |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2797 code->last = orig_start + ZMAX_NATIVE_SIZE; |
652 | 2798 translate_z80inst(&instbuf, context, address, 0); |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2799 code_info tmp2 = *code; |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2800 *code = tmp_code; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2801 if (!z80_is_terminal(&instbuf)) { |
652 | 2802 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2803 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst)); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2804 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
2805 z80_handle_deferred(context); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2806 return orig_start; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
2807 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2808 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2809 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2810 void translate_z80_stream(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2811 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2812 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2813 if (z80_get_native_address(context, address)) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2814 return; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2815 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2816 z80_options * opts = context->options; |
505
b7b7a1cab44a
The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2817 uint32_t start_address = address; |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
2818 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2819 do |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2820 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2821 z80inst inst; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2822 dprintf("translating Z80 code at address %X\n", address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2823 do { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2824 uint8_t * existing = z80_get_native_address(context, address); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2825 if (existing) { |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2826 jmp(&opts->gen.code, existing); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2827 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2828 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2829 uint8_t * encoded, *next; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2830 encoded = get_native_pointer(address, (void **)context->mem_pointers, &opts->gen); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2831 if (!encoded) { |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2832 code_info stub = z80_make_interp_stub(context, address); |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2833 z80_map_native_address(context, address, stub.cur, 1, stub.last - stub.cur); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2834 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2835 } |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2836 //make sure prologue is in a contiguous chunk of code |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
598
diff
changeset
|
2837 check_code_prologue(&opts->gen.code); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2838 next = z80_decode(encoded, &inst); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2839 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
2840 z80_disasm(&inst, disbuf, address); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2841 if (inst.op == Z80_NOP) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2842 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2843 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2844 printf("%X\t%s\n", address, disbuf); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2845 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2846 #endif |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2847 code_ptr start = opts->gen.code.cur; |
652 | 2848 translate_z80inst(&inst, context, address, 0); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2849 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2850 address += next-encoded; |
255
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents:
254
diff
changeset
|
2851 address &= 0xFFFF; |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
2852 } while (!z80_is_terminal(&inst)); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2853 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2854 if (opts->gen.deferred) { |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2855 address = opts->gen.deferred->address; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
2856 dprintf("defferred address: %X\n", address); |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
2857 } |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2858 } while (opts->gen.deferred); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2859 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2860 |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
2861 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider) |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2862 { |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2863 memset(options, 0, sizeof(*options)); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2864 |
653
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2865 options->gen.memmap = chunks; |
a18e3923481e
Remove some of the hard coded assumptions about the memory map from the CPU cores
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
2866 options->gen.memmap_chunks = num_chunks; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2867 options->gen.address_size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2868 options->gen.address_mask = 0xFFFF; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2869 options->gen.max_address = 0x10000; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2870 options->gen.bus_cycles = 3; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
2871 options->gen.clock_divider = clock_divider; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2872 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2873 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags); |
620
9d6fed6501ba
Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents:
601
diff
changeset
|
2874 options->gen.ram_flags_shift = 7; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2875 |
235
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Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2876 options->flags = 0; |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2877 #ifdef X86_64 |
235
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Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2878 options->regs[Z80_B] = BH; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2879 options->regs[Z80_C] = RBX; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
2880 options->regs[Z80_D] = CH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2881 options->regs[Z80_E] = RCX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2882 options->regs[Z80_H] = AH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2883 options->regs[Z80_L] = RAX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2884 options->regs[Z80_IXH] = DH; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2885 options->regs[Z80_IXL] = RDX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2886 options->regs[Z80_IYH] = -1; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
2887 options->regs[Z80_IYL] = R8; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2888 options->regs[Z80_I] = -1; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2889 options->regs[Z80_R] = RDI; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2890 options->regs[Z80_A] = R10; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2891 options->regs[Z80_BC] = RBX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2892 options->regs[Z80_DE] = RCX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2893 options->regs[Z80_HL] = RAX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2894 options->regs[Z80_SP] = R9; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2895 options->regs[Z80_AF] = -1; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2896 options->regs[Z80_IX] = RDX; |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
2897 options->regs[Z80_IY] = R8; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
2898 |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2899 options->gen.scratch1 = R13; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2900 options->gen.scratch2 = R14; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2901 #else |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2902 memset(options->regs, -1, sizeof(options->regs)); |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2903 options->regs[Z80_A] = RAX; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2904 options->regs[Z80_R] = AH; |
1048
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
2905 options->regs[Z80_H] = BH; |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
2906 options->regs[Z80_L] = RBX; |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
2907 options->regs[Z80_HL] = RBX; |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
2908 |
05ecef6c73b6
More efficient register usage in 32-bit mode
Michael Pavone <pavone@retrodev.com>
parents:
1047
diff
changeset
|
2909 options->regs[Z80_SP] = RDI; |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
2910 |
666
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2911 options->gen.scratch1 = RCX; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2912 options->gen.scratch2 = RDX; |
b68039895627
In theory, the Z80 core should work on 32-bit builds now; however, I suspect there is some code that cannot deal with most of the Z80 registers not having a native register so more work will be needed
Michael Pavone <pavone@retrodev.com>
parents:
665
diff
changeset
|
2913 #endif |
667
30ccf56842d6
All cycle counters are now based off the master clock. This seems to have messed up Z80 interrupt timing (music in Sonic 2 is too slow for instance), but things are generally working
Michael Pavone <pavone@retrodev.com>
parents:
666
diff
changeset
|
2914 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2915 options->gen.context_reg = RSI; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2916 options->gen.cycles = RBP; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2917 options->gen.limit = -1; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2918 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2919 options->gen.native_code_map = malloc(sizeof(native_map_slot)); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2920 memset(options->gen.native_code_map, 0, sizeof(native_map_slot)); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2921 options->gen.deferred = NULL; |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2922 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *)); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2923 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
2924 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2925 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2926 code_info *code = &options->gen.code; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2927 init_code_info(code); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2928 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2929 options->save_context_scratch = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2930 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2931 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2932 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2933 options->gen.save_context = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2934 for (int i = 0; i <= Z80_A; i++) |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2935 { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2936 int reg; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2937 uint8_t size; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2938 if (i < Z80_I) { |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2939 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2940 size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2941 } else { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2942 reg = i; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2943 size = SZ_B; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2944 } |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2945 if (reg == Z80_R) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2946 and_ir(code, 0x7F, options->regs[Z80_R], SZ_B); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2947 or_rrdisp(code, options->regs[Z80_R], options->gen.context_reg, zr_off(Z80_R), SZ_B); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2948 } else if (options->regs[reg] >= 0) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2949 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, zr_off(reg), size); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2950 if (reg == Z80_R) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2951 and_irdisp(code, 0x80, options->gen.context_reg, zr_off(reg), SZ_B); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2952 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2953 } |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2954 if (size == SZ_W) { |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2955 i++; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2956 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2957 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2958 if (options->regs[Z80_SP] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2959 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2960 } |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2961 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2962 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2963 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2964 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2965 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2966 options->load_context_scratch = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2967 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2968 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2969 options->gen.load_context = code->cur; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2970 for (int i = 0; i <= Z80_A; i++) |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2971 { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2972 int reg; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2973 uint8_t size; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2974 if (i < Z80_I) { |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2975 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2976 size = SZ_W; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2977 } else { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2978 reg = i; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2979 size = SZ_B; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2980 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2981 if (options->regs[reg] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2982 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2983 } |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2984 if (size == SZ_W) { |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2985 i++; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
2986 } |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2987 } |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2988 if (options->regs[Z80_SP] >= 0) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2989 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
2990 } |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2991 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
2992 sub_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2993 retn(code); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2994 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2995 options->native_addr = code->cur; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2996 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
2997 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2998 movzx_rr(code, options->gen.scratch1, options->gen.scratch1, SZ_W, SZ_D); |
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
2999 call_args(code, (code_ptr)z80_get_native_address_trans, 2, options->gen.context_reg, options->gen.scratch1); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3000 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3001 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3002 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3003 retn(code); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3004 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3005 uint32_t tmp_stack_off; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3006 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3007 options->gen.handle_cycle_limit = code->cur; |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3008 //calculate call/stack adjust size |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3009 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3010 call_noalign(code, options->gen.handle_cycle_limit); |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3011 uint32_t call_adjust_size = code->cur - options->gen.handle_cycle_limit; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3012 code->cur = options->gen.handle_cycle_limit; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3013 |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3014 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3015 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3016 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3017 code_ptr no_sync = code->cur+1; |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3018 jcc(code, CC_B, no_sync); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3019 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3020 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3021 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3022 call(code, options->save_context_scratch); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3023 tmp_stack_off = code->stack_off; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3024 pop_r(code, RAX); //return address in read/write func |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3025 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3026 pop_r(code, RBX); //return address in translated code |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3027 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3028 sub_ir(code, call_adjust_size, RAX, SZ_PTR); //adjust return address to point to the call + stack adjust that got us here |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3029 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3030 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
664
diff
changeset
|
3031 restore_callee_save_regs(code); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3032 //return to caller of z80_run |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3033 retn(code); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3034 |
598
faad1927d836
Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80
Michael Pavone <pavone@retrodev.com>
parents:
597
diff
changeset
|
3035 *no_sync = code->cur - (no_sync + 1); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3036 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3037 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3038 retn(code); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3039 code->stack_off = tmp_stack_off; |
652 | 3040 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3041 options->gen.handle_code_write = (code_ptr)z80_handle_code_write; |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3042 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3043 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc); |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3044 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3045 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3046 code_ptr skip_int = code->cur; |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3047 //calculate adjust size |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3048 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3049 uint32_t adjust_size = code->cur - skip_int; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3050 code->cur = skip_int; |
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3051 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3052 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3053 code_ptr skip_sync = code->cur + 1; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3054 jcc(code, CC_B, skip_sync); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3055 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3056 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3057 //save PC |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3058 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, pc), SZ_D); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3059 options->do_sync = code->cur; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3060 call(code, options->gen.save_context); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3061 tmp_stack_off = code->stack_off; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3062 //pop return address off the stack and save for resume later |
898
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3063 //pop_rind(code, options->gen.context_reg); |
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3064 pop_r(code, RAX); |
900
30efd12b1be1
Replace some hard-coded instruction length assumptions with a calculation so they will work properly on both 32-bit and 64-bit hosts
Michael Pavone <pavone@retrodev.com>
parents:
899
diff
changeset
|
3065 add_ir(code, adjust_size, RAX, SZ_PTR); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3066 add_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
898
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3067 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR); |
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3068 |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3069 //restore callee saved registers |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3070 restore_callee_save_regs(code); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3071 //return to caller of z80_run |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3072 retn(code); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3073 *skip_sync = code->cur - (skip_sync+1); |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3074 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3075 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3076 retn(code); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3077 code->stack_off = tmp_stack_off; |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3078 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3079 options->gen.handle_cycle_limit_int = code->cur; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3080 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3081 add_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3082 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3083 jcc(code, CC_B, skip_int); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3084 //set limit to the cycle limit |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3085 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.scratch2, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3086 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3087 neg_r(code, options->gen.cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3088 add_rr(code, options->gen.scratch2, options->gen.cycles, SZ_D); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3089 //disable interrupts |
591
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3090 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B); |
966b46c68942
Get Z80 core back into compileable state
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
|
3091 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3092 cycles(&options->gen, 7); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3093 //save return address (in scratch1) to Z80 stack |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3094 sub_ir(code, 2, options->regs[Z80_SP], SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3095 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3096 //we need to do check_cycles and cycles outside of the write_8 call |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3097 //so that the stack has the correct depth if we need to return to C |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3098 //for a synchronization |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3099 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3100 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3101 //save word to write before call to write_8_noinc |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3102 push_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3103 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3104 //restore word to write |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3105 pop_r(code, options->gen.scratch1); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3106 //write high byte to SP+1 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3107 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3108 add_ir(code, 1, options->gen.scratch2, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3109 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3110 check_cycles(&options->gen); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3111 cycles(&options->gen, 3); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3112 call(code, options->write_8_noinc); |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3113 //dispose of return address as we'll be jumping somewhere else |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3114 add_ir(code, 16, RSP, SZ_PTR); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3115 //TODO: Support interrupt mode 0 and 2 |
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3116 mov_ir(code, 0x38, options->gen.scratch1, SZ_W); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3117 call(code, options->native_addr); |
663
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
3118 mov_rrind(code, options->gen.scratch1, options->gen.context_reg, SZ_PTR); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3119 tmp_stack_off = code->stack_off; |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
664
diff
changeset
|
3120 restore_callee_save_regs(code); |
663
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
3121 //return to caller of z80_run to sync |
7a5461001242
Sync Z80 when taking an interrupt so that int_cycle gets updated
Michael Pavone <pavone@retrodev.com>
parents:
662
diff
changeset
|
3122 retn(code); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3123 code->stack_off = tmp_stack_off; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3124 |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3125 //HACK |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3126 options->gen.address_size = SZ_D; |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3127 options->gen.address_mask = 0xFF; |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3128 options->read_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, READ_8, NULL); |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3129 options->write_io = gen_mem_fun(&options->gen, io_chunks, num_io_chunks, WRITE_8, NULL); |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3130 options->gen.address_size = SZ_W; |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3131 options->gen.address_mask = 0xFFFF; |
652 | 3132 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3133 options->read_16 = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3134 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3135 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3136 //TODO: figure out how to handle the extra wait state for word reads to bank area |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3137 //may also need special handling to avoid too much stack depth when access is blocked |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3138 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3139 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3140 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3141 #ifndef X86_64 |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3142 //scratch 2 is a caller save register in 32-bit builds and may be clobbered by something called from the read8 fun |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3143 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3144 #endif |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3145 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3146 add_ir(code, 1, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3147 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3148 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3149 call(code, options->read_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3150 shl_ir(code, 8, options->gen.scratch1, SZ_W); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3151 #ifdef X86_64 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3152 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B); |
735
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3153 #else |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3154 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch1, SZ_B); |
539d12fa6a4d
Add a define in both the source and Makefile for enabling logging of z80 instruction address/cycle counts. Fix Z80 in/out instructions to eliminate assumptions about which registers are stored in native regs. Fix read_16 to not corrupt the low byte when the read has to call into a C function.
Michael Pavone <pavone@retrodev.com>
parents:
734
diff
changeset
|
3155 #endif |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3156 retn(code); |
652 | 3157 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3158 options->write_16_highfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3159 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3160 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3161 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3162 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3163 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3164 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3165 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3166 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3167 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3168 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3169 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3170 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3171 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3172 retn(code); |
652 | 3173 |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3174 options->write_16_lowfirst = code->cur; |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3175 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3176 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3177 push_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3178 push_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3179 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3180 pop_r(code, options->gen.scratch1); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3181 pop_r(code, options->gen.scratch2); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3182 add_ir(code, 1, options->gen.scratch2, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3183 shr_ir(code, 8, options->gen.scratch1, SZ_W); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3184 cycles(&options->gen, 3); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3185 check_cycles(&options->gen); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3186 //TODO: Check if we can get away with TCO here |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3187 call(code, options->write_8_noinc); |
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3188 retn(code); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3189 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3190 options->retrans_stub = code->cur; |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3191 tmp_stack_off = code->stack_off; |
899
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3192 //calculate size of patch |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3193 mov_ir(code, 0x7FFF, options->gen.scratch1, SZ_D); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3194 code->stack_off += sizeof(void *); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3195 if (code->stack_off & 0xF) { |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3196 sub_ir(code, 16 - (code->stack_off & 0xF), RSP, SZ_PTR); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3197 } |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3198 call_noalign(code, options->retrans_stub); |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3199 uint32_t patch_size = code->cur - options->retrans_stub; |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3200 code->cur = options->retrans_stub; |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3201 code->stack_off = tmp_stack_off; |
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3202 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3203 //pop return address |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3204 pop_r(code, options->gen.scratch2); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3205 add_ir(code, 16-sizeof(void*), RSP, SZ_PTR); |
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3206 code->stack_off = tmp_stack_off; |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3207 call(code, options->gen.save_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3208 //adjust pointer before move and call instructions that got us here |
899
07bfbbbb4b2e
Fix for Z80 retranslation post alignment rework
Michael Pavone <pavone@retrodev.com>
parents:
898
diff
changeset
|
3209 sub_ir(code, patch_size, options->gen.scratch2, SZ_PTR); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3210 push_r(code, options->gen.context_reg); |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3211 call_args(code, (code_ptr)z80_retranslate_inst, 3, options->gen.scratch1, options->gen.context_reg, options->gen.scratch2); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3212 pop_r(code, options->gen.context_reg); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3213 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3214 call(code, options->gen.load_context); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3215 jmp_r(code, options->gen.scratch1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3216 |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3217 options->run = (z80_run_fun)code->cur; |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3218 tmp_stack_off = code->stack_off; |
665
d0943769353b
Added functions to gen_x86 for saving and restoring callee save registers to better abstract over ABI differences between x86 and x86-64
Michael Pavone <pavone@retrodev.com>
parents:
664
diff
changeset
|
3219 save_callee_save_regs(code); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3220 #ifdef X86_64 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3221 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR); |
729
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3222 #else |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3223 mov_rdispr(code, RSP, 5 * sizeof(int32_t), options->gen.context_reg, SZ_PTR); |
9ef6db986982
Fix a bunch of assumptions about which Z80 registers are stored in native registers to make the x86-32 build less broken
Michael Pavone <pavone@retrodev.com>
parents:
716
diff
changeset
|
3224 #endif |
594
086de8692932
Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80
Michael Pavone <pavone@retrodev.com>
parents:
593
diff
changeset
|
3225 call(code, options->load_context_scratch); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3226 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3227 code_ptr no_extra = code->cur+1; |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3228 jcc(code, CC_Z, no_extra); |
898
2f1157f00dc6
Z80 core is now slightly less broken
Michael Pavone <pavone@retrodev.com>
parents:
895
diff
changeset
|
3229 sub_ir(code, 16-sizeof(void *), RSP, SZ_PTR); |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3230 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc)); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3231 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3232 *no_extra = code->cur - (no_extra + 1); |
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
592
diff
changeset
|
3233 jmp_rind(code, options->gen.context_reg); |
895
13388ab6d78a
Get Z80 core sort of working again post alignment change
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
3234 code->stack_off = tmp_stack_off; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3235 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3236 |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
506
diff
changeset
|
3237 void init_z80_context(z80_context * context, z80_options * options) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3238 { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3239 memset(context, 0, sizeof(*context)); |
360
c42fae88d346
Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error
Mike Pavone <pavone@retrodev.com>
parents:
335
diff
changeset
|
3240 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
parents:
257
diff
changeset
|
3241 context->static_code_map->base = NULL; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3242 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3243 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
627
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
3244 context->banked_code_map = malloc(sizeof(native_map_slot)); |
c5820734a5b6
Added some preliminary support for interpreting Z80 code from non-RAM addresses
Michael Pavone <pavone@retrodev.com>
parents:
626
diff
changeset
|
3245 memset(context->banked_code_map, 0, sizeof(native_map_slot)); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3246 context->options = options; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3247 context->int_cycle = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3248 context->int_pulse_start = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3249 context->int_pulse_end = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3250 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3251 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3252 void z80_run(z80_context * context, uint32_t target_cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3253 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3254 if (context->reset || context->busack) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3255 context->current_cycle = target_cycle; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3256 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3257 if (context->current_cycle < target_cycle) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3258 //busreq is sampled at the end of an m-cycle |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3259 //we can approximate that by running for a single m-cycle after a bus request |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3260 context->sync_cycle = context->busreq ? context->current_cycle + 3*context->options->gen.clock_divider : target_cycle; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3261 if (!context->native_pc) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3262 context->native_pc = z80_get_native_address_trans(context, context->pc); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3263 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3264 while (context->current_cycle < context->sync_cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3265 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3266 if (context->int_pulse_end < context->current_cycle || context->int_pulse_end == CYCLE_NEVER) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3267 z80_next_int_pulse(context); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3268 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3269 if (context->iff1) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3270 context->int_cycle = context->int_pulse_start < context->int_enable_cycle ? context->int_enable_cycle : context->int_pulse_start; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3271 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3272 context->int_cycle = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3273 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3274 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle; |
670
f4f3e74b0ce6
Restore Z80 interrupt pulse duration and make a small improvement to debug print output
Michael Pavone <pavone@retrodev.com>
parents:
668
diff
changeset
|
3275 dprintf("Running Z80 from cycle %d to cycle %d. Int cycle: %d (%d - %d)\n", context->current_cycle, context->sync_cycle, context->int_cycle, context->int_pulse_start, context->int_pulse_end); |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3276 context->options->run(context); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3277 dprintf("Z80 ran to cycle %d\n", context->current_cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3278 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3279 if (context->busreq) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3280 context->busack = 1; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3281 context->current_cycle = target_cycle; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3282 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3283 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3284 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3285 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3286 |
884
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3287 void z80_options_free(z80_options *opts) |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3288 { |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3289 free(opts->gen.native_code_map); |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3290 free(opts->gen.ram_inst_sizes); |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3291 free(opts); |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3292 } |
252dfd29831d
Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents:
854
diff
changeset
|
3293 |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3294 void z80_assert_reset(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3295 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3296 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3297 context->reset = 1; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3298 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3299 |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3300 void z80_clear_reset(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3301 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3302 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3303 if (context->reset) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3304 //TODO: Handle case where reset is not asserted long enough |
701
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3305 context->im = 0; |
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3306 context->iff1 = context->iff2 = 0; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3307 context->native_pc = NULL; |
701
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3308 context->extra_pc = NULL; |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3309 context->pc = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3310 context->reset = 0; |
676
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3311 if (context->busreq) { |
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3312 //TODO: Figure out appropriate delay |
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3313 context->busack = 1; |
41a399c11ef1
When going directly from reset to busreq, do not allow the Z80 to run
Michael Pavone <pavone@retrodev.com>
parents:
670
diff
changeset
|
3314 } |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3315 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3316 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3317 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3318 void z80_assert_busreq(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3319 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3320 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3321 context->busreq = 1; |
854
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3322 //this is an imperfect aproximation since most M-cycles take less tstates than the max |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3323 //and a short 3-tstate m-cycle can take an unbounded number due to wait states |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3324 if (context->current_cycle - cycle > MAX_MCYCLE_LENGTH * context->options->gen.clock_divider) { |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3325 context->busack = 1; |
adeb6465ad53
Improve timing of Z80 busack. Fixes a crash in Barkley: Shut Up and Jam. Also vastly improves the audio output of Stuck Somewhere in Time
Michael Pavone <pavone@retrodev.com>
parents:
844
diff
changeset
|
3326 } |
701
200ee73c7210
Remove/comment verbose logging added for tracking down sync bug
Michael Pavone <pavone@retrodev.com>
parents:
697
diff
changeset
|
3327 } |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3328 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3329 void z80_clear_busreq(z80_context * context, uint32_t cycle) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3330 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3331 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3332 context->busreq = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3333 context->busack = 0; |
844
74e161fe7d39
Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
842
diff
changeset
|
3334 //there appears to be at least a 1 Z80 cycle delay between busreq |
74e161fe7d39
Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
842
diff
changeset
|
3335 //being released and resumption of execution |
74e161fe7d39
Small tweaks to timing of 68K/Z80 interactions based on latest tests
Michael Pavone <pavone@retrodev.com>
parents:
842
diff
changeset
|
3336 context->current_cycle += context->options->gen.clock_divider; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3337 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3338 |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3339 uint8_t z80_get_busack(z80_context * context, uint32_t cycle) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3340 { |
668
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3341 z80_run(context, cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3342 return context->busack; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3343 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3344 |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3345 void z80_adjust_cycles(z80_context * context, uint32_t deduction) |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3346 { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3347 if (context->current_cycle < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3348 fprintf(stderr, "WARNING: Deduction of %u cycles when Z80 cycle counter is only %u\n", deduction, context->current_cycle); |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3349 context->current_cycle = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3350 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3351 context->current_cycle -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3352 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3353 if (context->int_enable_cycle != CYCLE_NEVER) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3354 if (context->int_enable_cycle < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3355 context->int_enable_cycle = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3356 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3357 context->int_enable_cycle -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3358 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3359 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3360 if (context->int_pulse_start != CYCLE_NEVER) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3361 if (context->int_pulse_end < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3362 context->int_pulse_start = context->int_pulse_end = CYCLE_NEVER; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3363 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3364 context->int_pulse_end -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3365 if (context->int_pulse_start < deduction) { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3366 context->int_pulse_start = 0; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3367 } else { |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3368 context->int_pulse_start -= deduction; |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3369 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3370 } |
5439ae7946ca
Made the Z80 core more contained by refactoring some code in blastem.c into z80_to_x86.c
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
3371 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3372 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3373 |
652 | 3374 uint32_t zbreakpoint_patch(z80_context * context, uint16_t address, code_ptr dst) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3375 { |
966
f765c2fc7508
Fix crash bug in Z80 debugger introduced with stack alignment changes
Michael Pavone <pavone@retrodev.com>
parents:
900
diff
changeset
|
3376 code_info code = {dst, dst+32}; |
659
759c38bf97f8
Minor Z80 core cleanup
Michael Pavone <pavone@retrodev.com>
parents:
657
diff
changeset
|
3377 mov_ir(&code, address, context->options->gen.scratch1, SZ_W); |
652 | 3378 call(&code, context->bp_stub); |
3379 return code.cur-dst; | |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3380 } |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3381 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3382 void zcreate_stub(z80_context * context) |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3383 { |
652 | 3384 z80_options * opts = context->options; |
3385 code_info *code = &opts->gen.code; | |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
884
diff
changeset
|
3386 uint32_t start_stack_off = code->stack_off; |
652 | 3387 check_code_prologue(code); |
3388 context->bp_stub = code->cur; | |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3389 |
682 | 3390 //Calculate length of prologue |
652 | 3391 check_cycles_int(&opts->gen, 0); |
3392 int check_int_size = code->cur-context->bp_stub; | |
3393 code->cur = context->bp_stub; | |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3394 |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3395 //Calculate length of patch |
652 | 3396 int patch_size = zbreakpoint_patch(context, 0, code->cur); |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3397 |
682 | 3398 //Save context and call breakpoint handler |
652 | 3399 call(code, opts->gen.save_context); |
3400 push_r(code, opts->gen.scratch1); | |
657
92ce5ea5ffc9
Use call_args and call_args_abi in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
653
diff
changeset
|
3401 call_args_abi(code, context->bp_handler, 2, opts->gen.context_reg, opts->gen.scratch1); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
3402 mov_rr(code, RAX, opts->gen.context_reg, SZ_PTR); |
682 | 3403 //Restore context |
652 | 3404 call(code, opts->gen.load_context); |
3405 pop_r(code, opts->gen.scratch1); | |
682 | 3406 //do prologue stuff |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3407 or_rr(code, opts->gen.cycles, opts->gen.cycles, SZ_D); |
652 | 3408 uint8_t * jmp_off = code->cur+1; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
1046
diff
changeset
|
3409 jcc(code, CC_NS, code->cur + 7); |
652 | 3410 pop_r(code, opts->gen.scratch1); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
3411 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR); |
652 | 3412 push_r(code, opts->gen.scratch1); |
3413 jmp(code, opts->gen.handle_cycle_limit_int); | |
3414 *jmp_off = code->cur - (jmp_off+1); | |
682 | 3415 //jump back to body of translated instruction |
652 | 3416 pop_r(code, opts->gen.scratch1); |
664
bca748422bf0
Use SZ_PTR instead of SZ_Q in Z80 core for 32-bit compat
Michael Pavone <pavone@retrodev.com>
parents:
663
diff
changeset
|
3417 add_ir(code, check_int_size - patch_size, opts->gen.scratch1, SZ_PTR); |
652 | 3418 jmp_r(code, opts->gen.scratch1); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
parents:
884
diff
changeset
|
3419 code->stack_off = start_stack_off; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3420 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3421 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3422 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3423 { |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3424 context->bp_handler = bp_handler; |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3425 uint8_t bit = 1 << (address % 8); |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3426 if (!(bit & context->breakpoint_flags[address / 8])) { |
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3427 context->breakpoint_flags[address / 8] |= bit; |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3428 if (!context->bp_stub) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3429 zcreate_stub(context); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3430 } |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3431 uint8_t * native = z80_get_native_address(context, address); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3432 if (native) { |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3433 zbreakpoint_patch(context, address, native); |
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3434 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3435 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3436 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
3437 |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3438 void zremove_breakpoint(z80_context * context, uint16_t address) |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3439 { |
819
ab017fb09e77
Added support for an IO memory map in Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
792
diff
changeset
|
3440 context->breakpoint_flags[address / 8] &= ~(1 << (address % 8)); |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3441 uint8_t * native = z80_get_native_address(context, address); |
626
7c46891a29b1
Properly handle Z80 breakpoints on self-modifying code and setting Z80 breakpoints before the Z80 program has been loaded
Michael Pavone <pavone@retrodev.com>
parents:
625
diff
changeset
|
3442 if (native) { |
652 | 3443 z80_options * opts = context->options; |
3444 code_info tmp_code = opts->gen.code; | |
3445 opts->gen.code.cur = native; | |
3446 opts->gen.code.last = native + 16; | |
3447 check_cycles_int(&opts->gen, address); | |
3448 opts->gen.code = tmp_code; | |
792
724bbec47f86
Use a new fatal_error function instead of calling fprintf and exit for fatal errors. This new function more gracefully handles the case in which BlastEm was not started from a terminal or disconnected from ther terminal (Windows).
Michael Pavone <pavone@retrodev.com>
parents:
755
diff
changeset
|
3449 } |
366
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3450 } |
836585d389b8
Partial implementation of Z80 debugger
Mike Pavone <pavone@retrodev.com>
parents:
363
diff
changeset
|
3451 |