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Revert change to VBLANK flag timing based on new direct color DMA test
author Mike Pavone <pavone@retrodev.com>
date Sun, 08 Sep 2013 20:48:33 -0700
parents e9b6fe443bf2
children 6221f8f534fa
comparison
equal deleted inserted replaced
458:848a3db9d0b0 459:c49ecf575784
1562 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { 1562 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) {
1563 value |= 0x10; 1563 value |= 0x10;
1564 } 1564 }
1565 uint32_t line= context->cycles / MCLKS_LINE; 1565 uint32_t line= context->cycles / MCLKS_LINE;
1566 uint32_t linecyc = context->cycles % MCLKS_LINE; 1566 uint32_t linecyc = context->cycles % MCLKS_LINE;
1567 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE) || context->cycles < (context->latched_mode & BIT_H40 ? 16*4 : 16*5)) { 1567 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) {
1568 value |= 0x8; 1568 value |= 0x8;
1569 } 1569 }
1570 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { 1570 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) {
1571 value |= 0x4; 1571 value |= 0x4;
1572 } 1572 }
1574 value |= 0x2; 1574 value |= 0x2;
1575 } 1575 }
1576 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify 1576 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify
1577 value |= 0x1; 1577 value |= 0x1;
1578 } 1578 }
1579 //printf("status read at cycle %d returned %X\n", context->cycles, value);
1579 //TODO: Sprite overflow, sprite collision, odd frame flag 1580 //TODO: Sprite overflow, sprite collision, odd frame flag
1580 return value; 1581 return value;
1581 } 1582 }
1582 1583
1583 uint16_t vdp_data_port_read(vdp_context * context) 1584 uint16_t vdp_data_port_read(vdp_context * context)