Mercurial > repos > blastem
annotate vdp.c @ 459:c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Sun, 08 Sep 2013 20:48:33 -0700 |
| parents | e9b6fe443bf2 |
| children | 6221f8f534fa |
| rev | line source |
|---|---|
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1 #include "vdp.h" |
| 75 | 2 #include "blastem.h" |
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3 #include <stdlib.h> |
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4 #include <string.h> |
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5 #include "render.h" |
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6 |
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7 #define NTSC_ACTIVE 225 |
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8 #define PAL_ACTIVE 241 |
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9 #define BUF_BIT_PRIORITY 0x40 |
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10 #define MAP_BIT_PRIORITY 0x8000 |
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11 #define MAP_BIT_H_FLIP 0x800 |
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12 #define MAP_BIT_V_FLIP 0x1000 |
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13 |
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14 #define SCROLL_BUFFER_SIZE 32 |
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15 #define SCROLL_BUFFER_MASK (SCROLL_BUFFER_SIZE-1) |
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16 #define SCROLL_BUFFER_DRAW (SCROLL_BUFFER_SIZE/2) |
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17 |
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18 #define FIFO_SIZE 4 |
| 40 | 19 |
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20 #define MCLKS_SLOT_H40 16 |
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21 #define MCLKS_SLOT_H32 20 |
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22 #define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after |
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23 #define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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24 #define HSYNC_SLOT_H40 21 |
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25 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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26 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
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27 #define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) |
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28 #define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) |
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29 #define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) |
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30 |
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31 int32_t color_map[1 << 12]; |
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32 uint8_t levels[] = {0, 27, 49, 71, 87, 103, 119, 130, 146, 157, 174, 190, 206, 228, 255}; |
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33 |
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34 uint8_t debug_base[][3] = { |
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35 {127, 127, 127}, //BG |
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36 {0, 0, 127}, //A |
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37 {127, 0, 0}, //Window |
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38 {0, 127, 0}, //B |
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39 {127, 0, 127} //Sprites |
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40 }; |
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41 |
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42 uint8_t color_map_init_done; |
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43 |
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44 void init_vdp_context(vdp_context * context) |
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45 { |
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46 memset(context, 0, sizeof(*context)); |
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47 context->vdpmem = malloc(VRAM_SIZE); |
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48 memset(context->vdpmem, 0, VRAM_SIZE); |
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49 context->oddbuf = context->framebuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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50 memset(context->framebuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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51 context->evenbuf = malloc(FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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52 memset(context->evenbuf, 0, FRAMEBUF_ENTRIES * (render_depth() / 8)); |
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53 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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54 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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55 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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56 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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57 context->sprite_draws = MAX_DRAWS; |
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58 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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59 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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60 context->b32 = render_depth() == 32; |
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61 if (!color_map_init_done) { |
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62 uint8_t b,g,r; |
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63 for (uint16_t color = 0; color < (1 << 12); color++) { |
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64 if (color & FBUF_SHADOW) { |
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65 b = levels[(color >> 9) & 0x7]; |
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66 g = levels[(color >> 5) & 0x7]; |
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67 r = levels[(color >> 1) & 0x7]; |
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68 } else if(color & FBUF_HILIGHT) { |
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69 b = levels[((color >> 9) & 0x7) + 7]; |
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70 g = levels[((color >> 5) & 0x7) + 7]; |
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71 r = levels[((color >> 1) & 0x7) + 7]; |
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72 } else { |
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73 b = levels[(color >> 8) & 0xE]; |
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74 g = levels[(color >> 4) & 0xE]; |
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75 r = levels[color & 0xE]; |
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76 } |
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77 color_map[color] = render_map_color(r, g, b); |
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78 } |
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79 color_map_init_done = 1; |
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80 } |
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81 for (uint8_t color = 0; color < (1 << (3 + 1 + 1 + 1)); color++) |
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82 { |
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83 uint8_t src = color & DBG_SRC_MASK; |
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84 if (src > DBG_SRC_S) { |
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85 context->debugcolors[color] = 0; |
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86 } else { |
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87 uint8_t r,g,b; |
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88 b = debug_base[src][0]; |
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89 g = debug_base[src][1]; |
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90 r = debug_base[src][2]; |
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91 if (color & DBG_PRIORITY) |
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92 { |
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93 if (b) { |
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94 b += 48; |
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95 } |
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96 if (g) { |
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97 g += 48; |
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98 } |
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99 if (r) { |
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100 r += 48; |
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101 } |
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102 } |
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103 if (color & DBG_SHADOW) { |
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104 b /= 2; |
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105 g /= 2; |
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106 r /=2 ; |
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107 } |
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108 if (color & DBG_HILIGHT) { |
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109 if (b) { |
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110 b += 72; |
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111 } |
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112 if (g) { |
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113 g += 72; |
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114 } |
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115 if (r) { |
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116 r += 72; |
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117 } |
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118 } |
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119 context->debugcolors[color] = render_map_color(r, g, b); |
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120 } |
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121 } |
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122 } |
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123 |
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124 void render_sprite_cells(vdp_context * context) |
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125 { |
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126 if (context->cur_slot >= context->sprite_draws) { |
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127 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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128 |
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129 uint16_t dir; |
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130 int16_t x; |
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131 if (d->h_flip) { |
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132 x = d->x_pos + 7; |
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133 dir = -1; |
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134 } else { |
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135 x = d->x_pos; |
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136 dir = 1; |
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137 } |
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138 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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139 context->cur_slot--; |
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140 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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141 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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142 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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143 } |
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144 x += dir; |
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145 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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146 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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147 } |
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148 x += dir; |
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149 } |
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150 } |
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151 } |
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152 |
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153 void vdp_print_sprite_table(vdp_context * context) |
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154 { |
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155 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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156 uint16_t current_index = 0; |
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157 uint8_t count = 0; |
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158 do { |
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159 uint16_t address = current_index * 8 + sat_address; |
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160 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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161 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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162 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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163 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
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164 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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165 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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166 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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167 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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168 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
|
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169 current_index = link; |
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170 count++; |
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171 } while (current_index != 0 && count < 80); |
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172 } |
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173 |
|
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174 void vdp_print_reg_explain(vdp_context * context) |
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175 { |
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176 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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177 printf("**Mode Group**\n" |
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178 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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179 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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180 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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181 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
|
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182 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
|
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183 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
|
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184 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
|
327
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185 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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186 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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187 hscroll[context->regs[REG_MODE_3] & 0x3], |
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188 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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189 printf("\n**Table Group**\n" |
|
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190 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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191 "03: %.2X | Window Name Table: $%.4X\n" |
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192 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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193 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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194 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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195 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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196 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
|
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197 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
|
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198 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
|
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199 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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200 char * sizes[] = {"32", "64", "invalid", "128"}; |
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201 printf("\n**Misc Group**\n" |
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202 "07: %.2X | Backdrop Color: $%X\n" |
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203 "0A: %.2X | H-Int Counter: %u\n" |
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204 "0F: %.2X | Auto-increment: $%X\n" |
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205 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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206 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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207 context->regs[REG_HINT], context->regs[REG_HINT], |
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208 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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209 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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210 printf("\n**Internal Group**\n" |
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211 "Address: %X\n" |
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212 "CD: %X\n" |
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213 "Pending: %s\n", |
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214 context->address, context->cd, (context->flags & FLAG_PENDING) ? "true" : "false"); |
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215 |
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216 //TODO: Window Group, DMA Group |
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217 } |
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218 |
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219 void scan_sprite_table(uint32_t line, vdp_context * context) |
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220 { |
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221 if (context->sprite_index && context->slot_counter) { |
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222 line += 1; |
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223 line &= 0xFF; |
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224 uint16_t ymask, ymin; |
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225 uint8_t height_mult; |
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226 if (context->double_res) { |
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227 line *= 2; |
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228 if (context->framebuf != context->oddbuf) { |
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229 line++; |
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230 } |
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231 ymask = 0x3FF; |
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232 ymin = 256; |
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233 height_mult = 16; |
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234 } else { |
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235 ymask = 0x1FF; |
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236 ymin = 128; |
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237 height_mult = 8; |
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238 } |
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239 context->sprite_index &= 0x7F; |
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240 if (context->latched_mode & BIT_H40) { |
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241 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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242 context->sprite_index = 0; |
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243 return; |
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244 } |
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245 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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246 context->sprite_index = 0; |
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247 return; |
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248 } |
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249 //TODO: Read from SAT cache rather than from VRAM |
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250 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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251 uint16_t address = context->sprite_index * 8 + sat_address; |
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252 line += ymin; |
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253 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
|
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254 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
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255 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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256 if (y <= line && line < (y + height)) { |
|
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257 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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258 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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259 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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260 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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261 } |
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262 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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263 if (context->sprite_index && context->slot_counter) |
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264 { |
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265 address = context->sprite_index * 8 + sat_address; |
|
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266 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & ymask; |
|
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267 height = ((context->vdpmem[address+2] & 0x3) + 1) * height_mult; |
|
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268 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
|
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269 if (y <= line && line < (y + height)) { |
|
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270 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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271 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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272 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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273 context->sprite_info_list[context->slot_counter].y = y-ymin; |
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274 } |
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275 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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276 } |
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277 } |
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278 } |
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279 |
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280 void read_sprite_x(uint32_t line, vdp_context * context) |
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281 { |
|
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282 if (context->cur_slot >= context->slot_counter) { |
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283 if (context->sprite_draws) { |
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284 line += 1; |
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285 line &= 0xFF; |
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286 //in tiles |
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287 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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288 //in pixels |
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289 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
|
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290 if (context->double_res) { |
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291 line *= 2; |
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292 if (context->framebuf != context->oddbuf) { |
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293 line++; |
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294 } |
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295 height *= 2; |
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296 } |
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297 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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298 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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299 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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300 uint8_t row; |
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301 if (tileinfo & MAP_BIT_V_FLIP) { |
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302 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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303 } else { |
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304 row = line-context->sprite_info_list[context->cur_slot].y; |
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305 } |
|
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306 uint16_t address; |
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307 if (context->double_res) { |
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308 address = ((tileinfo & 0x3FF) << 6) + row * 4; |
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309 } else { |
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310 address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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311 } |
|
323
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312 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
|
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313 if (x) { |
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314 context->flags |= FLAG_CAN_MASK; |
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315 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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316 context->flags |= FLAG_MASKED; |
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317 } |
|
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318 |
|
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319 context->flags &= ~FLAG_DOT_OFLOW; |
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320 int16_t i; |
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321 if (context->flags & FLAG_MASKED) { |
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322 for (i=0; i < width && context->sprite_draws; i++) { |
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323 --context->sprite_draws; |
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324 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
|
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325 } |
|
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326 } else { |
|
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327 x -= 128; |
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328 int16_t base_x = x; |
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329 int16_t dir; |
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330 if (tileinfo & MAP_BIT_H_FLIP) { |
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331 x += (width-1) * 8; |
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332 dir = -8; |
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333 } else { |
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334 dir = 8; |
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335 } |
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336 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
|
35
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337 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
|
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338 --context->sprite_draws; |
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339 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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340 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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341 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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342 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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343 } |
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344 } |
|
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345 if (i < width) { |
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346 context->flags |= FLAG_DOT_OFLOW; |
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347 } |
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348 context->cur_slot--; |
|
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349 } else { |
|
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350 context->flags |= FLAG_DOT_OFLOW; |
|
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351 } |
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352 } |
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353 } |
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354 |
|
427
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355 void write_cram(vdp_context * context, uint16_t address, uint16_t value) |
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356 { |
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357 uint16_t addr = (address/2) & (CRAM_SIZE-1); |
|
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358 context->cram[addr] = value; |
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359 context->colors[addr] = color_map[value & 0xEEE]; |
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360 context->colors[addr + CRAM_SIZE] = color_map[(value & 0xEEE) | FBUF_SHADOW]; |
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361 context->colors[addr + CRAM_SIZE*2] = color_map[(value & 0xEEE) | FBUF_HILIGHT]; |
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362 } |
|
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363 |
|
54
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364 #define VRAM_READ 0 |
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365 #define VRAM_WRITE 1 |
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366 #define CRAM_READ 8 |
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367 #define CRAM_WRITE 3 |
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368 #define VSRAM_READ 4 |
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369 #define VSRAM_WRITE 5 |
| 75 | 370 #define DMA_START 0x20 |
|
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371 |
|
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372 void external_slot(vdp_context * context) |
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373 { |
| 75 | 374 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
| 375 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
| 376 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
|
149
139e5dcd6aa3
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diff
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|
377 if(context->flags & FLAG_DMA_RUN) { |
| 75 | 378 uint16_t dma_len; |
| 379 switch(context->regs[REG_DMASRC_H] & 0xC0) | |
|
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380 { |
| 75 | 381 //68K -> VDP |
| 382 case 0: | |
| 383 case 0x40: | |
|
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384 switch(context->dma_cd & 0xF) |
| 75 | 385 { |
| 386 case VRAM_WRITE: | |
| 387 if (context->flags & FLAG_DMA_PROG) { | |
| 388 context->vdpmem[context->address ^ 1] = context->dma_val; | |
| 389 context->flags &= ~FLAG_DMA_PROG; | |
| 390 } else { | |
| 391 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 392 context->vdpmem[context->address] = context->dma_val >> 8; | |
| 393 context->flags |= FLAG_DMA_PROG; | |
| 394 } | |
| 395 break; | |
|
426
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diff
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|
396 case CRAM_WRITE: { |
|
427
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diff
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|
397 write_cram(context, context->address, read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L])); |
|
151
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398 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles); |
| 75 | 399 break; |
|
426
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400 } |
| 75 | 401 case VSRAM_WRITE: |
| 402 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 403 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 404 } | |
| 405 break; | |
|
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|
406 } |
|
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407 break; |
| 75 | 408 //Fill |
| 409 case 0x80: | |
|
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|
410 switch(context->dma_cd & 0xF) |
| 75 | 411 { |
| 412 case VRAM_WRITE: | |
| 413 //Charles MacDonald's VDP doc says that the low byte gets written first | |
| 142 | 414 context->vdpmem[context->address] = context->dma_val; |
| 415 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF); | |
| 75 | 416 break; |
|
427
2802318c14e1
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426
diff
changeset
|
417 case CRAM_WRITE: |
|
450
3758bcdae5de
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438
diff
changeset
|
418 write_cram(context, context->address, context->dma_val); |
|
337
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334
diff
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|
419 //printf("CRAM DMA Fill | %X set to %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->cycles); |
| 75 | 420 break; |
| 421 case VSRAM_WRITE: | |
| 422 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 423 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 424 } | |
| 425 break; | |
| 426 } | |
|
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427 break; |
| 75 | 428 //Copy |
| 429 case 0xC0: | |
| 430 if (context->flags & FLAG_DMA_PROG) { | |
|
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431 switch(context->dma_cd & 0xF) |
| 75 | 432 { |
| 433 case VRAM_WRITE: | |
| 434 context->vdpmem[context->address] = context->dma_val; | |
| 435 break; | |
|
426
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436 case CRAM_WRITE: { |
|
427
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426
diff
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|
437 write_cram(context, context->address, context->dma_val); |
|
337
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diff
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|
438 //printf("CRAM DMA Copy | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], context->regs[REG_DMASRC_L] & (CRAM_SIZE-1), context->cycles); |
| 75 | 439 break; |
|
426
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424
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|
440 } |
| 75 | 441 case VSRAM_WRITE: |
| 442 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 443 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 444 } | |
| 445 break; | |
| 446 } | |
| 447 context->flags &= ~FLAG_DMA_PROG; | |
| 448 } else { | |
| 449 //I assume, that DMA copy copies from the same RAM as the destination | |
| 450 //but it's possible I'm mistaken | |
|
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|
451 switch(context->dma_cd & 0xF) |
| 75 | 452 { |
| 453 case VRAM_WRITE: | |
| 454 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
| 455 break; | |
| 456 case CRAM_WRITE: | |
| 457 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
| 458 break; | |
| 459 case VSRAM_WRITE: | |
| 460 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
| 461 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
| 462 } else { | |
| 463 context->dma_val = 0; | |
| 464 } | |
| 465 break; | |
| 466 } | |
| 467 context->flags |= FLAG_DMA_PROG; | |
|
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|
468 } |
|
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|
469 break; |
|
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|
470 } |
| 75 | 471 if (!(context->flags & FLAG_DMA_PROG)) { |
| 472 context->address += context->regs[REG_AUTOINC]; | |
| 473 context->regs[REG_DMASRC_L] += 1; | |
| 135 | 474 if (!context->regs[REG_DMASRC_L]) { |
| 475 context->regs[REG_DMASRC_M] += 1; | |
| 476 } | |
| 75 | 477 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
| 478 context->regs[REG_DMALEN_H] = dma_len >> 8; | |
| 479 context->regs[REG_DMALEN_L] = dma_len; | |
| 480 if (!dma_len) { | |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
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452
diff
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|
481 //printf("DMA end at cycle %d\n", context->cycles); |
| 75 | 482 context->flags &= ~FLAG_DMA_RUN; |
| 483 } | |
|
54
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diff
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|
484 } |
|
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diff
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|
485 } else { |
| 75 | 486 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
| 487 if (context->fifo_cur != start && start->cycle <= context->cycles) { | |
|
450
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Mike Pavone <pavone@retrodev.com>
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|
488 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START) && (context->regs[REG_DMASRC_H] & 0xC0) == 0x80) { |
|
453
b491df8bdbc0
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Mike Pavone <pavone@retrodev.com>
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452
diff
changeset
|
489 //printf("DMA fill started at %d\n", context->cycles); |
| 75 | 490 context->flags |= FLAG_DMA_RUN; |
| 491 context->dma_val = start->value; | |
| 138 | 492 context->address = start->address; //undo auto-increment |
|
131
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109
diff
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|
493 context->dma_cd = context->cd; |
| 75 | 494 } else { |
| 138 | 495 switch (start->cd & 0xF) |
| 75 | 496 { |
| 497 case VRAM_WRITE: | |
| 498 if (start->partial) { | |
| 499 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); | |
| 138 | 500 context->vdpmem[start->address ^ 1] = start->value; |
| 75 | 501 } else { |
| 502 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); | |
| 138 | 503 context->vdpmem[start->address] = start->value >> 8; |
| 75 | 504 start->partial = 1; |
| 505 //skip auto-increment and removal of entry from fifo | |
| 506 return; | |
| 507 } | |
| 508 break; | |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
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424
diff
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|
509 case CRAM_WRITE: { |
|
151
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Implement MULU/MULS and DIVU/DIVS
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149
diff
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|
510 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
|
427
2802318c14e1
Refactor duplicated CRAM writing code and fix a bug in the process
Mike Pavone <pavone@retrodev.com>
parents:
426
diff
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|
511 write_cram(context, start->address, start->value); |
| 75 | 512 break; |
|
426
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424
diff
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|
513 } |
| 75 | 514 case VSRAM_WRITE: |
| 138 | 515 if (((start->address/2) & 63) < VSRAM_SIZE) { |
| 75 | 516 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
| 138 | 517 context->vsram[(start->address/2) & 63] = start->value; |
| 75 | 518 } |
| 519 break; | |
| 520 } | |
| 138 | 521 //context->address += context->regs[REG_AUTOINC]; |
| 75 | 522 } |
| 523 fifo_entry * cur = start+1; | |
| 524 if (cur < context->fifo_cur) { | |
| 525 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); | |
| 526 } | |
| 527 context->fifo_cur -= 1; | |
| 528 } else { | |
| 529 context->flags |= FLAG_UNUSED_SLOT; | |
| 530 } | |
|
54
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diff
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|
531 } |
|
20
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|
532 } |
|
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533 |
| 40 | 534 #define WINDOW_RIGHT 0x80 |
| 535 #define WINDOW_DOWN 0x80 | |
| 536 | |
|
25
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diff
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|
537 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
|
20
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|
538 { |
|
417
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415
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|
539 uint16_t window_line_shift, v_offset_mask, vscroll_shift; |
|
414
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|
540 if (context->double_res) { |
|
413
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|
541 line *= 2; |
|
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|
542 if (context->framebuf != context->oddbuf) { |
|
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|
543 line++; |
|
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|
544 } |
|
417
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415
diff
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|
545 window_line_shift = 4; |
|
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Fix window layer in double res interlace mode
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415
diff
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|
546 v_offset_mask = 0xF; |
|
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diff
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|
547 vscroll_shift = 4; |
|
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diff
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|
548 } else { |
|
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415
diff
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|
549 window_line_shift = 3; |
|
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Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
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diff
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|
550 v_offset_mask = 0x7; |
|
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Fix window layer in double res interlace mode
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diff
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|
551 vscroll_shift = 3; |
|
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
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413
diff
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|
552 } |
| 40 | 553 if (!vsram_off) { |
| 554 uint16_t left_col, right_col; | |
| 555 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
|
41
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40
diff
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|
556 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
|
e591004487bc
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40
diff
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|
557 right_col = 42; |
|
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40
diff
changeset
|
558 } else { |
| 40 | 559 left_col = 0; |
| 560 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
| 561 if (right_col) { | |
| 562 right_col += 2; | |
| 563 } | |
| 564 } | |
|
41
e591004487bc
More correct window support, maybe
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40
diff
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|
565 uint16_t top_line, bottom_line; |
|
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40
diff
changeset
|
566 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
|
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
567 top_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
|
acdd6c5240fe
Fix window layer in double res interlace mode
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parents:
415
diff
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|
568 bottom_line = context->double_res ? 481 : 241; |
|
41
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
569 } else { |
|
e591004487bc
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40
diff
changeset
|
570 top_line = 0; |
|
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
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415
diff
changeset
|
571 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) << window_line_shift; |
|
41
e591004487bc
More correct window support, maybe
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parents:
40
diff
changeset
|
572 } |
|
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
573 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
|
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
574 uint16_t address = context->regs[REG_WINDOW] << 10; |
|
e591004487bc
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parents:
40
diff
changeset
|
575 uint16_t line_offset, offset, mask; |
|
e591004487bc
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40
diff
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|
576 if (context->latched_mode & BIT_H40) { |
|
e591004487bc
More correct window support, maybe
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40
diff
changeset
|
577 address &= 0xF000; |
|
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
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415
diff
changeset
|
578 line_offset = (((line) >> vscroll_shift) * 64 * 2) & 0xFFF; |
|
41
e591004487bc
More correct window support, maybe
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parents:
40
diff
changeset
|
579 mask = 0x7F; |
|
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
580 |
|
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
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40
diff
changeset
|
581 } else { |
|
e591004487bc
More correct window support, maybe
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parents:
40
diff
changeset
|
582 address &= 0xF800; |
|
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
583 line_offset = (((line) >> vscroll_shift) * 32 * 2) & 0xFFF; |
|
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
584 mask = 0x3F; |
|
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
585 } |
|
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
586 if (context->double_res) { |
|
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
587 mask <<= 1; |
|
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
588 mask |= 1; |
|
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
589 } |
|
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
590 offset = address + line_offset + (((column - 2) * 2) & mask); |
|
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
591 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
592 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
|
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
Mike Pavone <pavone@retrodev.com>
parents:
41
diff
changeset
|
593 offset = address + line_offset + (((column - 1) * 2) & mask); |
|
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
594 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
417
acdd6c5240fe
Fix window layer in double res interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
415
diff
changeset
|
595 context->v_offset = (line) & v_offset_mask; |
|
41
e591004487bc
More correct window support, maybe
Mike Pavone <pavone@retrodev.com>
parents:
40
diff
changeset
|
596 context->flags |= FLAG_WINDOW; |
|
e591004487bc
More correct window support, maybe
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parents:
40
diff
changeset
|
597 return; |
| 40 | 598 } |
| 599 context->flags &= ~FLAG_WINDOW; | |
| 600 } | |
|
20
f664eeb55cb4
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parents:
diff
changeset
|
601 uint16_t vscroll; |
|
f664eeb55cb4
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parents:
diff
changeset
|
602 switch(context->regs[REG_SCROLL] & 0x30) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
603 { |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
604 case 0: |
|
f664eeb55cb4
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parents:
diff
changeset
|
605 vscroll = 0xFF; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
606 break; |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
607 case 0x10: |
|
f664eeb55cb4
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parents:
diff
changeset
|
608 vscroll = 0x1FF; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
609 break; |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
610 case 0x20: |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
611 //TODO: Verify this behavior |
|
f664eeb55cb4
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parents:
diff
changeset
|
612 vscroll = 0; |
|
f664eeb55cb4
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parents:
diff
changeset
|
613 break; |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
614 case 0x30: |
|
f664eeb55cb4
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parents:
diff
changeset
|
615 vscroll = 0x3FF; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
616 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
617 } |
|
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
618 if (context->double_res) { |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
619 vscroll <<= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
620 vscroll |= 1; |
|
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
621 } |
|
454
e9b6fe443bf2
Fix per-column scrolling bug
Mike Pavone <pavone@retrodev.com>
parents:
453
diff
changeset
|
622 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? (column-2)&63 : 0) + vsram_off] + line); |
|
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
623 context->v_offset = vscroll & v_offset_mask; |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
624 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
|
414
51ee0f117365
Fix vscroll calculation in double resultion interlace mode
Mike Pavone <pavone@retrodev.com>
parents:
413
diff
changeset
|
625 vscroll >>= vscroll_shift; |
|
20
f664eeb55cb4
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parents:
diff
changeset
|
626 uint16_t hscroll_mask; |
|
f664eeb55cb4
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parents:
diff
changeset
|
627 uint16_t v_mul; |
|
f664eeb55cb4
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parents:
diff
changeset
|
628 switch(context->regs[REG_SCROLL] & 0x3) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
629 { |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
630 case 0: |
|
108
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631 hscroll_mask = 0x1F; |
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632 v_mul = 64; |
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633 break; |
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634 case 0x1: |
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635 hscroll_mask = 0x3F; |
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636 v_mul = 128; |
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637 break; |
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638 case 0x2: |
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639 //TODO: Verify this behavior |
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640 hscroll_mask = 0; |
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641 v_mul = 0; |
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642 break; |
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643 case 0x3: |
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644 hscroll_mask = 0x7F; |
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645 v_mul = 256; |
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646 break; |
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647 } |
| 28 | 648 uint16_t hscroll, offset; |
| 649 for (int i = 0; i < 2; i++) { | |
|
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650 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
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651 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
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652 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
| 28 | 653 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
| 654 if (i) { | |
| 655 context->col_2 = col_val; | |
| 656 } else { | |
| 657 context->col_1 = col_val; | |
| 658 } | |
| 659 } | |
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660 } |
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661 |
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662 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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663 { |
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664 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
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665 } |
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666 |
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667 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
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668 { |
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669 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
|
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670 } |
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671 |
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672 void render_map(uint16_t col, uint8_t * tmp_buf, uint8_t offset, vdp_context * context) |
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673 { |
|
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674 uint16_t address; |
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675 uint8_t shift, add; |
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676 if (context->double_res) { |
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677 address = ((col & 0x3FF) << 6); |
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678 shift = 1; |
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679 add = context->framebuf != context->oddbuf ? 1 : 0; |
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680 } else { |
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681 address = ((col & 0x7FF) << 5); |
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682 shift = 0; |
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683 add = 0; |
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684 } |
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685 if (col & MAP_BIT_V_FLIP) { |
|
414
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686 address += 28 - 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
|
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687 } else { |
|
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688 address += 4 * context->v_offset/*((context->v_offset << shift) + add)*/; |
|
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689 } |
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690 uint16_t pal_priority = (col >> 9) & 0x70; |
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691 int32_t dir; |
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692 if (col & MAP_BIT_H_FLIP) { |
|
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693 offset += 7; |
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694 offset &= SCROLL_BUFFER_MASK; |
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695 dir = -1; |
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696 } else { |
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697 dir = 1; |
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698 } |
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699 for (uint32_t i=0; i < 4; i++, address++) |
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|
700 { |
|
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701 tmp_buf[offset] = pal_priority | (context->vdpmem[address] >> 4); |
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702 offset += dir; |
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703 offset &= SCROLL_BUFFER_MASK; |
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704 tmp_buf[offset] = pal_priority | (context->vdpmem[address] & 0xF); |
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|
705 offset += dir; |
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|
706 offset &= SCROLL_BUFFER_MASK; |
|
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707 } |
|
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708 } |
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|
709 |
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710 void render_map_1(vdp_context * context) |
|
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|
711 { |
|
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712 render_map(context->col_1, context->tmp_buf_a, context->buf_a_off, context); |
|
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713 } |
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714 |
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715 void render_map_2(vdp_context * context) |
|
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|
716 { |
|
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717 render_map(context->col_2, context->tmp_buf_a, context->buf_a_off+8, context); |
|
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718 } |
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|
719 |
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720 void render_map_3(vdp_context * context) |
|
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|
721 { |
|
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722 render_map(context->col_1, context->tmp_buf_b, context->buf_b_off, context); |
|
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723 } |
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|
724 |
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|
725 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
|
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726 { |
|
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|
727 if (line >= 240) { |
|
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|
728 return; |
|
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|
729 } |
|
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730 render_map(context->col_2, context->tmp_buf_b, context->buf_b_off+8, context); |
|
426
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|
731 uint16_t *dst; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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424
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|
732 uint32_t *dst32; |
|
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733 uint8_t *sprite_buf, *plane_a, *plane_b; |
|
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734 int plane_a_off, plane_b_off; |
|
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|
735 if (col) |
|
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|
736 { |
|
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diff
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|
737 col-=2; |
|
426
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diff
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|
738 if (context->b32) { |
|
add9e2f5c0e3
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739 dst32 = context->framebuf; |
|
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|
740 dst32 += line * 320 + col * 8; |
|
add9e2f5c0e3
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|
741 } else { |
|
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Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
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diff
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|
742 dst = context->framebuf; |
|
add9e2f5c0e3
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|
743 dst += line * 320 + col * 8; |
|
add9e2f5c0e3
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|
744 } |
|
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|
745 sprite_buf = context->linebuf + col * 8; |
|
437
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parents:
436
diff
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|
746 uint8_t a_src, src; |
| 40 | 747 if (context->flags & FLAG_WINDOW) { |
|
436
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|
748 plane_a_off = context->buf_a_off; |
|
437
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parents:
436
diff
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|
749 a_src = DBG_SRC_W; |
| 40 | 750 } else { |
|
436
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parents:
427
diff
changeset
|
751 plane_a_off = context->buf_a_off - (context->hscroll_a & 0xF); |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
752 a_src = DBG_SRC_A; |
| 40 | 753 } |
|
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
754 plane_b_off = context->buf_b_off - (context->hscroll_b & 0xF); |
| 30 | 755 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
|
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
756 |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
757 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
|
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
758 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
759 uint8_t pixel; |
|
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
760 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
|
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
761 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
762 uint32_t * colors = context->colors; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
763 src = 0; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
764 uint8_t sprite_color = *sprite_buf & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
765 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
|
232
54873acb982e
Shadow and higlight operators were switched
Mike Pavone <pavone@retrodev.com>
parents:
230
diff
changeset
|
766 if (sprite_color == 0x3F) { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
767 colors += CRAM_SIZE; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
768 src = DBG_SHADOW; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
769 } else { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
770 colors += CRAM_SIZE*2; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
771 src = DBG_HILIGHT; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
772 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
773 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
774 pixel = *plane_a; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
775 src |= a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
776 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
777 pixel = *plane_b; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
778 src |= DBG_SRC_B; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
779 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
780 pixel = *plane_a; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
781 src |= a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
782 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
783 pixel = *plane_b; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
784 src |= DBG_SRC_B; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
785 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
786 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
787 src |= DBG_SRC_BG; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
788 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
789 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
790 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
791 pixel = *sprite_buf; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
792 src = DBG_SRC_S; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
793 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
794 pixel = *plane_a; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
795 src = a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
796 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
797 pixel = *plane_b; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
798 src = DBG_SRC_B; |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
799 } else { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
800 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
801 colors += CRAM_SIZE; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
802 src = DBG_SHADOW; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
803 } |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
804 if (*sprite_buf & 0xF) { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
805 pixel = *sprite_buf; |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
806 if (*sprite_buf & 0xF == 0xE) { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
807 colors = context->colors; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
808 src = DBG_SRC_S; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
809 } else { |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
810 src |= DBG_SRC_S; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
811 } |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
812 } else if (*plane_a & 0xF) { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
813 pixel = *plane_a; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
814 src |= a_src; |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
815 } else if (*plane_b & 0xF){ |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
816 pixel = *plane_b; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
817 src |= DBG_SRC_B; |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
818 } else { |
|
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
819 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
820 src |= DBG_SRC_BG; |
|
233
9d10669f2579
Less broken implementation of shadow/highlight
Mike Pavone <pavone@retrodev.com>
parents:
232
diff
changeset
|
821 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
822 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
823 } |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
824 pixel &= 0x3F; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
825 uint32_t outpixel; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
826 if (context->debug) { |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
827 outpixel = context->debugcolors[src]; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
828 } else { |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
829 outpixel = colors[pixel]; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
830 } |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
831 if (context->b32) { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
832 *(dst32++) = outpixel; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
833 } else { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
834 *(dst++) = outpixel; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
835 } |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
836 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
838 } else { |
|
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
839 for (int i = 0; i < 16; ++plane_a_off, ++plane_b_off, ++sprite_buf, ++i) { |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
840 uint8_t pixel; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
841 src = 0; |
|
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
842 plane_a = context->tmp_buf_a + (plane_a_off & SCROLL_BUFFER_MASK); |
|
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
843 plane_b = context->tmp_buf_b + (plane_b_off & SCROLL_BUFFER_MASK); |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
844 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
845 pixel = *sprite_buf; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
846 src = DBG_SRC_S; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
847 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
848 pixel = *plane_a; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
849 src = a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
850 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
851 pixel = *plane_b; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
852 src = DBG_SRC_B; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
853 } else if (*sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
854 pixel = *sprite_buf; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
855 src = DBG_SRC_S; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
856 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
857 pixel = *plane_a; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
858 src = a_src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
859 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
860 pixel = *plane_b; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
861 src = DBG_SRC_B; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
862 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
863 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
864 src = DBG_SRC_BG; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
865 } |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
866 uint32_t outpixel; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
867 if (context->debug) { |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
868 outpixel = context->debugcolors[src]; |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
869 } else { |
|
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
870 outpixel = context->colors[pixel & 0x3F]; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
871 } |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
872 if (context->b32) { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
873 *(dst32++) = outpixel; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
874 } else { |
|
437
afbea09d7fb4
Restore one of the VDP debugging modes
Mike Pavone <pavone@retrodev.com>
parents:
436
diff
changeset
|
875 *(dst++) = outpixel; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
876 } |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
877 //*dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
878 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 } else { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 //dst = context->framebuf + line * 320; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 //sprite_buf = context->linebuf + col * 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 //end = dst + 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 } |
|
436
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
887 context->buf_a_off = (context->buf_a_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
|
e341fd5aa996
Implement the scroll ring buffer properly without memcpy
Mike Pavone <pavone@retrodev.com>
parents:
427
diff
changeset
|
888 context->buf_b_off = (context->buf_b_off + SCROLL_BUFFER_DRAW) & SCROLL_BUFFER_MASK; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 external_slot(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 uint16_t address; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 uint32_t mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 case 0: |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
950 context->cur_slot = MAX_DRAWS-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 memset(context->linebuf, 0, LINEBUF_SIZE); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 case 2: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
955 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
956 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
957 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
958 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
959 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 //sprite attribute table scan starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 case 4: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
963 render_sprite_cells( context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 context->sprite_index = 0x80; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 context->slot_counter = MAX_SPRITES_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 case 13: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 case 14: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 case 19: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 //!HSYNC asserted |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
985 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 case 22: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
987 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
988 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
991 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
992 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 case 26: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 case 27: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 case 28: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 case 31: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 case 32: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 case 33: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 case 34: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1004 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1006 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1007 case 35: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 mask = 0; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1010 if (context->regs[REG_MODE_3] & 0x2) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1011 mask |= 0xF8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 if (context->regs[REG_MODE_3] & 0x1) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 mask |= 0x7; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1015 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 line &= mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 address += line * 4; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1018 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1020 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1021 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1022 case 36: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 //!HSYNC high |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 case 37: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1025 case 38: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1026 case 39: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1027 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1029 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1030 case 40: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 read_map_scroll_a(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 case 41: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1034 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 case 42: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 render_map_1(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 case 43: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 render_map_2(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1043 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1044 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1045 case 44: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1046 read_map_scroll_b(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1047 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1048 case 45: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1049 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1050 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1051 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1052 case 46: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 render_map_3(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 case 47: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 render_map_output(line, 0, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 //reverse context slot counter so it counts the number of sprite slots |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 //filled rather than the number of available slots |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1061 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
|
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
1062 context->cur_slot = MAX_SPRITES_LINE-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 context->sprite_draws = MAX_DRAWS; |
|
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
1064 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1065 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1066 COLUMN_RENDER_BLOCK(2, 48) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 COLUMN_RENDER_BLOCK(4, 56) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 COLUMN_RENDER_BLOCK(6, 64) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 COLUMN_RENDER_BLOCK(10, 80) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 COLUMN_RENDER_BLOCK(12, 88) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 COLUMN_RENDER_BLOCK(14, 96) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 COLUMN_RENDER_BLOCK(18, 112) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 COLUMN_RENDER_BLOCK(20, 120) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 COLUMN_RENDER_BLOCK(22, 128) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 COLUMN_RENDER_BLOCK(26, 144) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 COLUMN_RENDER_BLOCK(28, 152) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 COLUMN_RENDER_BLOCK(30, 160) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 COLUMN_RENDER_BLOCK(34, 176) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 COLUMN_RENDER_BLOCK(36, 184) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 COLUMN_RENDER_BLOCK(38, 192) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 case 208: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 case 209: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1089 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1090 default: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 //leftovers from HSYNC clock change nonsense |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 { |
| 37 | 1098 uint16_t address; |
| 1099 uint32_t mask; | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1100 switch(linecyc) |
|
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parents:
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|
1101 { |
|
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|
1102 //sprite render to line buffer starts |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1103 case 0: |
| 37 | 1104 context->cur_slot = MAX_DRAWS_H32-1; |
| 1105 memset(context->linebuf, 0, LINEBUF_SIZE); | |
|
20
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|
1106 case 1: |
|
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parents:
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|
1107 case 2: |
| 37 | 1108 case 3: |
|
329
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Implement first line/last line weirdness in VDP
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parents:
328
diff
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|
1109 if (line == 0xFF) { |
|
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diff
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|
1110 external_slot(context); |
|
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Implement first line/last line weirdness in VDP
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diff
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|
1111 } else { |
|
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328
diff
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|
1112 render_sprite_cells(context); |
|
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Implement first line/last line weirdness in VDP
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|
1113 } |
|
20
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changeset
|
1114 break; |
| 37 | 1115 //sprite attribute table scan starts |
|
20
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diff
changeset
|
1116 case 4: |
| 37 | 1117 render_sprite_cells( context); |
| 1118 context->sprite_index = 0x80; | |
| 1119 context->slot_counter = MAX_SPRITES_LINE_H32; | |
| 1120 scan_sprite_table(line, context); | |
|
20
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 break; |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 case 5: |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1123 case 6: |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 case 7: |
|
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parents:
diff
changeset
|
1125 case 8: |
|
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parents:
diff
changeset
|
1126 case 9: |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1127 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1128 case 11: |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1129 case 12: |
|
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diff
changeset
|
1130 case 13: |
| 37 | 1131 render_sprite_cells(context); |
| 1132 scan_sprite_table(line, context); | |
|
20
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Mostly broken VDP core and savestate viewer
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diff
changeset
|
1133 case 14: |
| 37 | 1134 external_slot(context); |
|
20
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 case 15: |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1137 case 16: |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1138 case 17: |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 case 18: |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 case 19: |
| 37 | 1141 //HSYNC start |
|
20
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parents:
diff
changeset
|
1142 case 20: |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1143 case 21: |
|
f664eeb55cb4
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parents:
diff
changeset
|
1144 case 22: |
|
f664eeb55cb4
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parents:
diff
changeset
|
1145 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1146 case 24: |
|
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parents:
diff
changeset
|
1147 case 25: |
|
f664eeb55cb4
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parents:
diff
changeset
|
1148 case 26: |
| 37 | 1149 render_sprite_cells(context); |
| 1150 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
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parents:
diff
changeset
|
1151 break; |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 case 27: |
| 37 | 1153 external_slot(context); |
|
20
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parents:
diff
changeset
|
1154 break; |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1155 case 28: |
| 37 | 1156 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
| 1157 mask = 0; | |
| 1158 if (context->regs[REG_MODE_3] & 0x2) { | |
| 1159 mask |= 0xF8; | |
| 1160 } | |
| 1161 if (context->regs[REG_MODE_3] & 0x1) { | |
| 1162 mask |= 0x7; | |
| 1163 } | |
| 1164 line &= mask; | |
| 1165 address += line * 4; | |
| 1166 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
| 1167 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
| 1168 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1170 case 29: |
|
f664eeb55cb4
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parents:
diff
changeset
|
1171 case 30: |
|
f664eeb55cb4
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parents:
diff
changeset
|
1172 case 31: |
| 37 | 1173 case 32: |
| 1174 render_sprite_cells(context); | |
| 1175 scan_sprite_table(line, context); | |
|
20
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1176 break; |
| 37 | 1177 //!HSYNC high |
|
20
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1178 case 33: |
| 37 | 1179 read_map_scroll_a(0, line, context); |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1180 break; |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1181 case 34: |
| 37 | 1182 render_sprite_cells(context); |
| 1183 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1184 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1185 case 35: |
| 37 | 1186 render_map_1(context); |
| 1187 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1188 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1189 case 36: |
| 37 | 1190 render_map_2(context); |
| 1191 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1192 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1193 case 37: |
| 37 | 1194 read_map_scroll_b(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1195 break; |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1196 case 38: |
| 37 | 1197 render_sprite_cells(context); |
| 1198 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1199 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 case 39: |
| 37 | 1201 render_map_3(context); |
| 1202 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 case 40: |
| 37 | 1205 render_map_output(line, 0, context); |
| 1206 scan_sprite_table(line, context);//Just a guess | |
| 1207 //reverse context slot counter so it counts the number of sprite slots | |
| 1208 //filled rather than the number of available slots | |
| 1209 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
| 1210 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
| 1211 context->sprite_draws = MAX_DRAWS_H32; | |
| 1212 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 break; |
| 37 | 1214 COLUMN_RENDER_BLOCK(2, 41) |
| 1215 COLUMN_RENDER_BLOCK(4, 49) | |
| 1216 COLUMN_RENDER_BLOCK(6, 57) | |
| 1217 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
| 1218 COLUMN_RENDER_BLOCK(10, 73) | |
| 1219 COLUMN_RENDER_BLOCK(12, 81) | |
| 1220 COLUMN_RENDER_BLOCK(14, 89) | |
| 1221 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
| 1222 COLUMN_RENDER_BLOCK(18, 105) | |
| 1223 COLUMN_RENDER_BLOCK(20, 113) | |
| 1224 COLUMN_RENDER_BLOCK(22, 121) | |
| 1225 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
| 1226 COLUMN_RENDER_BLOCK(26, 137) | |
| 1227 COLUMN_RENDER_BLOCK(28, 145) | |
| 1228 COLUMN_RENDER_BLOCK(30, 153) | |
| 1229 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 case 169: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 case 170: |
| 37 | 1232 external_slot(context); |
|
20
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1233 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1235 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1236 void latch_mode(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 { |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1238 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 } |
|
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parents:
diff
changeset
|
1240 |
|
330
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1241 int is_refresh(vdp_context * context, uint32_t slot) |
|
54
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Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1242 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1243 if (context->latched_mode & BIT_H40) { |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1244 //TODO: Determine behavior for DMA fills and copies |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1245 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210 |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1246 || ((context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) != VRAM_WRITE)) && ( |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1247 //both of the missed reads occurred right next to each other, but there seems |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1248 //to be some buffering involved, these values produce similar artifacts |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1249 //to what I see on my Model 2 |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1250 slot == 34 || slot == 66 || slot == 99 || slot == 130 || slot == 162 || slot == 194)); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1251 } else { |
|
189
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
1252 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
|
191
1b4d856b067a
Fixes for direct color dma stuff
Mike Pavone <pavone@retrodev.com>
parents:
190
diff
changeset
|
1253 //These numbers are guesses based on H40 numbers |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1254 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152 |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1255 || ((context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) != VRAM_WRITE)) && ( |
|
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1256 slot == 21 || slot == 53 || slot == 85 || slot == 117 || slot == 149)); |
|
189
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
1257 //The numbers below are the refresh slots during active display |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1258 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1259 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1260 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1261 |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1262 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1263 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1264 if (line > 0) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1265 line -= 1; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1266 int starti = -1; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1267 if (context->latched_mode & BIT_H40) { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1268 if (slot >= 50 && slot < 210) { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
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|
1269 uint32_t x = (slot-50)*2; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1270 starti = line * 320 + x; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1271 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1272 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1273 if (slot >= 43 && slot < 171) { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1274 uint32_t x = (slot-43)*2; |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1275 starti = line * 320 + x; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1276 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1277 } |
|
426
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1278 if (starti >= 0) { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1279 if (context->b32) { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1280 uint32_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1281 uint32_t * start = context->framebuf; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1282 start += starti; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1283 for (int i = 0; i < 2; i++) { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1284 *(start++) = color; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1285 } |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1286 } else { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1287 uint16_t color = context->colors[context->regs[REG_BG_COLOR] & 0x3F]; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1288 uint16_t * start = context->framebuf; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1289 start += starti; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1290 for (int i = 0; i < 2; i++) { |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1291 *(start++) = color; |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1292 } |
|
add9e2f5c0e3
Make VDP render in native pixel format of the renderer for a modest performance gain and to make it easier to use OpenGL for rendering
Mike Pavone <pavone@retrodev.com>
parents:
424
diff
changeset
|
1293 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1294 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1295 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1296 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1297 |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1298 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1299 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1300 while(context->cycles < target_cycles) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1301 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1302 uint32_t line = context->cycles / MCLKS_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1303 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
334
4c91470e1a53
Only latch video mode at the very beginning of the frame to avoid problems with the cycle count getting out of sync with what I expect
Mike Pavone <pavone@retrodev.com>
parents:
333
diff
changeset
|
1304 if (!context->cycles) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1305 latch_mode(context); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1306 } |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1307 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1308 if (linecyc == 0) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
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291
diff
changeset
|
1309 if (line <= 1 || line >= active_lines) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
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291
diff
changeset
|
1310 context->hint_counter = context->regs[REG_HINT]; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1311 } else if (context->hint_counter) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1312 context->hint_counter--; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1313 } else { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1314 context->flags2 |= FLAG2_HINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1315 context->hint_counter = context->regs[REG_HINT]; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
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291
diff
changeset
|
1316 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1317 } else if(line == active_lines) { |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1318 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1319 if (linecyc == intcyc) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1320 context->flags2 |= FLAG2_VINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1321 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1322 } |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1323 uint32_t inccycles, slot; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1324 if (context->latched_mode & BIT_H40){ |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1325 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1326 slot = linecyc/MCLKS_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1327 inccycles = MCLKS_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1328 } else if(linecyc < MCLK_WEIRD_END) { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1329 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1330 { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1331 case 0: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1332 inccycles = 19; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1333 slot = 0; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1334 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1335 case 19: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1336 slot = 1; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1337 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1338 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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diff
changeset
|
1339 case 39: |
|
57453d3d8be4
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329
diff
changeset
|
1340 slot = 2; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1341 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1342 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1343 case 59: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1344 slot = 3; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1345 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1346 break; |
|
57453d3d8be4
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329
diff
changeset
|
1347 case 79: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
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331
diff
changeset
|
1348 slot = 4; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1349 inccycles = 18; |
|
57453d3d8be4
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parents:
329
diff
changeset
|
1350 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1351 case 97: |
|
57453d3d8be4
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Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1352 slot = 5; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1353 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1354 break; |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1355 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1356 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1357 inccycles = 20; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1358 break; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1359 case 137: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1360 slot = 7; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1361 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1362 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1363 case 157: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1364 slot = 8; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1365 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1366 break; |
|
57453d3d8be4
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329
diff
changeset
|
1367 case 175: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1368 slot = 9; |
|
330
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|
1369 inccycles = 20; |
|
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diff
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|
1370 break; |
|
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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diff
changeset
|
1371 case 195: |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1372 slot = 10; |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
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|
1373 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
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|
1374 break; |
|
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329
diff
changeset
|
1375 case 215: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
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|
1376 slot = 11; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1377 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1378 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1379 case 235: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1380 slot = 12; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1381 inccycles = 18; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1382 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1383 case 253: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
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|
1384 slot = 13; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
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329
diff
changeset
|
1385 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1386 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1387 case 273: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1388 slot = 14; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1389 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1390 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1391 case 293: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1392 slot = 15; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1393 inccycles = 20; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1394 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1395 case 313: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1396 slot = 16; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1397 inccycles = 19; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1398 break; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1399 default: |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1400 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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parents:
329
diff
changeset
|
1401 exit(1); |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1402 } |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1403 slot += HSYNC_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1404 } else { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1405 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1406 inccycles = MCLKS_SLOT_H40; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1407 } |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1408 } else { |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1409 inccycles = MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1410 slot = linecyc/MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1411 } |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
1412 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1413 //first sort-of active line is treated as 255 internally |
|
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1414 //it's used for gathering sprite info for line |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1415 line = (line - 1) & 0xFF; |
|
450
3758bcdae5de
Fix bug that caused a DMA fill to start after another DMA operation completed if the FIFO is not empty
Mike Pavone <pavone@retrodev.com>
parents:
438
diff
changeset
|
1416 |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1417 //Convert to slot number |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1418 if (context->latched_mode & BIT_H40){ |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1419 vdp_h40(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1420 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1421 vdp_h32(line, slot, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1422 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1423 } else { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1424 if (!is_refresh(context, slot)) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1425 external_slot(context); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1426 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1427 if (line < active_lines) { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1428 check_render_bg(context, line, slot); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1429 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1430 } |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1431 context->cycles += inccycles; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1432 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1433 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1434 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1435 uint32_t vdp_run_to_vblank(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1436 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1437 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1438 vdp_run_context(context, target_cycles); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1439 return context->cycles; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1440 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1441 |
| 75 | 1442 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
| 1443 { | |
| 1444 for(;;) { | |
| 1445 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
| 1446 if (!dmalen) { | |
| 1447 dmalen = 0x10000; | |
| 1448 } | |
| 1449 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
| 1450 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
| 1451 //DMA copies take twice as long to complete since they require a read and a write | |
| 1452 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
| 1453 min_dma_complete *= 2; | |
| 1454 } | |
| 1455 min_dma_complete += context->cycles; | |
| 1456 if (target_cycles < min_dma_complete) { | |
| 1457 vdp_run_context(context, target_cycles); | |
| 1458 return; | |
| 1459 } else { | |
| 1460 vdp_run_context(context, min_dma_complete); | |
| 1461 if (!(context->flags & FLAG_DMA_RUN)) { | |
| 1462 return; | |
| 1463 } | |
| 1464 } | |
| 1465 } | |
| 1466 } | |
| 1467 | |
| 1468 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1469 { |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1470 //printf("control port write: %X at %d\n", value, context->cycles); |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1471 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1472 return -1; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1473 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1474 if (context->flags & FLAG_PENDING) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1475 context->address = (context->address & 0x3FFF) | (value << 14); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1476 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
| 75 | 1477 context->flags &= ~FLAG_PENDING; |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1478 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
|
327
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1479 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
|
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1480 // |
| 75 | 1481 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
| 1482 //DMA copy or 68K -> VDP, transfer starts immediately | |
| 1483 context->flags |= FLAG_DMA_RUN; | |
|
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
Mike Pavone <pavone@retrodev.com>
parents:
109
diff
changeset
|
1484 context->dma_cd = context->cd; |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1485 //printf("DMA start at cycle %d\n", context->cycles); |
| 75 | 1486 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
|
327
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1487 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
| 75 | 1488 return 1; |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1489 } else { |
|
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1490 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
| 75 | 1491 } |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1492 } else { |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1493 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
| 75 | 1494 } |
|
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1495 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1496 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1497 if ((value & 0xC000) == 0x8000) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1498 //Register write |
|
3b79cbcf6846
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43
diff
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|
1499 uint8_t reg = (value >> 8) & 0x1F; |
|
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43
diff
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|
1500 if (reg < VDP_REGS) { |
|
453
b491df8bdbc0
Adjust VBLANK flag and refresh timing to be in line with logic analyzer and visual observations of direct color DMA demos. Remove debug print statements.
Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1501 //printf("register %d set to %X\n", reg, value & 0xFF); |
|
54
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43
diff
changeset
|
1502 context->regs[reg] = value; |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
Mike Pavone <pavone@retrodev.com>
parents:
149
diff
changeset
|
1503 if (reg == REG_MODE_2) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
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parents:
149
diff
changeset
|
1504 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
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149
diff
changeset
|
1505 } |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
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337
diff
changeset
|
1506 if (reg == REG_MODE_4) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
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337
diff
changeset
|
1507 context->double_res = (value & (BIT_INTERLACE | BIT_DOUBLE_RES)) == (BIT_INTERLACE | BIT_DOUBLE_RES); |
|
415
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1508 if (!context->double_res) { |
|
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1509 context->framebuf = context->oddbuf; |
|
8c60c8c09a0f
Fix sprite y mask in interlace mode. Fix framebuffer selection when switching out of interlace mode.
Mike Pavone <pavone@retrodev.com>
parents:
414
diff
changeset
|
1510 } |
|
413
36fbbced25c2
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337
diff
changeset
|
1511 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1512 } |
|
3b79cbcf6846
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43
diff
changeset
|
1513 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1514 context->flags |= FLAG_PENDING; |
|
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Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1515 context->address = (context->address &0xC000) | (value & 0x3FFF); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1516 context->cd = (context->cd &0x3C) | (value >> 14); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1517 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1518 } |
| 75 | 1519 return 0; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1520 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1521 |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
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143
diff
changeset
|
1522 int vdp_data_port_write(vdp_context * context, uint16_t value) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1523 { |
|
453
b491df8bdbc0
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Mike Pavone <pavone@retrodev.com>
parents:
452
diff
changeset
|
1524 //printf("data port write: %X at %d\n", value, context->cycles); |
|
149
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143
diff
changeset
|
1525 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1526 return -1; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
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143
diff
changeset
|
1527 } |
|
139e5dcd6aa3
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Mike Pavone <pavone@retrodev.com>
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143
diff
changeset
|
1528 if (!(context->cd & 1)) { |
|
139e5dcd6aa3
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Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1529 //ignore writes when cd is configured for read |
|
139e5dcd6aa3
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Mike Pavone <pavone@retrodev.com>
parents:
143
diff
changeset
|
1530 return 0; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
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143
diff
changeset
|
1531 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1532 context->flags &= ~FLAG_PENDING; |
|
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1533 /*if (context->fifo_cur == context->fifo_end) { |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1534 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
|
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
parents:
108
diff
changeset
|
1535 }*/ |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1536 while (context->fifo_cur == context->fifo_end) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1537 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1538 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1539 context->fifo_cur->cycle = context->cycles; |
| 138 | 1540 context->fifo_cur->address = context->address; |
|
54
3b79cbcf6846
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43
diff
changeset
|
1541 context->fifo_cur->value = value; |
| 138 | 1542 context->fifo_cur->cd = context->cd; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1543 context->fifo_cur->partial = 0; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1544 context->fifo_cur++; |
| 138 | 1545 context->address += context->regs[REG_AUTOINC]; |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
Mike Pavone <pavone@retrodev.com>
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143
diff
changeset
|
1546 return 0; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
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43
diff
changeset
|
1547 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1548 |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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parents:
43
diff
changeset
|
1549 uint16_t vdp_control_port_read(vdp_context * context) |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1550 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1551 context->flags &= ~FLAG_PENDING; |
|
3b79cbcf6846
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parents:
43
diff
changeset
|
1552 uint16_t value = 0x3400; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1553 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1554 value |= 0x200; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1555 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1556 if (context->fifo_cur == context->fifo_end) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1557 value |= 0x100; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
changeset
|
1558 } |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1559 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1560 value |= 0x80; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1561 } |
|
36fbbced25c2
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Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1562 if ((context->regs[REG_MODE_4] & BIT_INTERLACE) && context->framebuf == context->oddbuf) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1563 value |= 0x10; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1564 } |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1565 uint32_t line= context->cycles / MCLKS_LINE; |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1566 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1567 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1568 value |= 0x8; |
|
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1569 } |
|
331
de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
Mike Pavone <pavone@retrodev.com>
parents:
330
diff
changeset
|
1570 if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { |
|
318
789f2f5f2277
Implement hblank flag in status register
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317
diff
changeset
|
1571 value |= 0x4; |
|
789f2f5f2277
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317
diff
changeset
|
1572 } |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1573 if (context->flags & FLAG_DMA_RUN) { |
|
141
576f55711d8d
Fix DMA in progress flag in VDP status register
Mike Pavone <pavone@retrodev.com>
parents:
138
diff
changeset
|
1574 value |= 0x2; |
| 75 | 1575 } |
|
317
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1576 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
|
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1577 value |= 0x1; |
|
e5e8b48ad157
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Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1578 } |
|
459
c49ecf575784
Revert change to VBLANK flag timing based on new direct color DMA test
Mike Pavone <pavone@retrodev.com>
parents:
454
diff
changeset
|
1579 //printf("status read at cycle %d returned %X\n", context->cycles, value); |
|
318
789f2f5f2277
Implement hblank flag in status register
Mike Pavone <pavone@retrodev.com>
parents:
317
diff
changeset
|
1580 //TODO: Sprite overflow, sprite collision, odd frame flag |
|
54
3b79cbcf6846
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43
diff
changeset
|
1581 return value; |
|
3b79cbcf6846
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43
diff
changeset
|
1582 } |
|
3b79cbcf6846
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43
diff
changeset
|
1583 |
|
3b79cbcf6846
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43
diff
changeset
|
1584 uint16_t vdp_data_port_read(vdp_context * context) |
|
3b79cbcf6846
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diff
changeset
|
1585 { |
|
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43
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changeset
|
1586 context->flags &= ~FLAG_PENDING; |
| 138 | 1587 if (context->cd & 1) { |
|
54
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43
diff
changeset
|
1588 return 0; |
|
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43
diff
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|
1589 } |
|
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43
diff
changeset
|
1590 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
|
3b79cbcf6846
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43
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changeset
|
1591 context->flags &= ~FLAG_UNUSED_SLOT; |
|
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43
diff
changeset
|
1592 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
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43
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changeset
|
1593 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
3b79cbcf6846
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diff
changeset
|
1594 } |
|
3b79cbcf6846
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diff
changeset
|
1595 uint16_t value = 0; |
| 138 | 1596 switch (context->cd & 0xF) |
|
54
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43
diff
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|
1597 { |
|
3b79cbcf6846
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43
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changeset
|
1598 case VRAM_READ: |
|
3b79cbcf6846
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43
diff
changeset
|
1599 value = context->vdpmem[context->address] << 8; |
|
3b79cbcf6846
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changeset
|
1600 context->flags &= ~FLAG_UNUSED_SLOT; |
|
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43
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changeset
|
1601 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
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43
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changeset
|
1602 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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diff
changeset
|
1603 } |
|
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43
diff
changeset
|
1604 value |= context->vdpmem[context->address ^ 1]; |
|
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43
diff
changeset
|
1605 break; |
|
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43
diff
changeset
|
1606 case CRAM_READ: |
|
3b79cbcf6846
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43
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changeset
|
1607 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
|
3b79cbcf6846
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43
diff
changeset
|
1608 break; |
|
3b79cbcf6846
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43
diff
changeset
|
1609 case VSRAM_READ: |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1610 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1611 value = context->vsram[context->address & 63]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1612 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1613 break; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1614 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1615 context->address += context->regs[REG_AUTOINC]; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1616 return value; |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1617 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1618 |
| 137 | 1619 uint16_t vdp_hv_counter_read(vdp_context * context) |
| 1620 { | |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1621 //TODO: deal with clock adjustemnts handled in vdp_run_context |
| 137 | 1622 uint32_t line= context->cycles / MCLKS_LINE; |
| 1623 if (!line) { | |
| 1624 line = 0xFF; | |
| 1625 } else { | |
| 1626 line--; | |
| 1627 if (line > 0xEA) { | |
| 1628 line = (line + 0xFA) & 0xFF; | |
| 1629 } | |
| 1630 } | |
| 1631 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
| 1632 if (context->latched_mode & BIT_H40) { | |
|
332
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1633 uint32_t slot; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1634 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1635 slot = linecyc/MCLKS_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1636 } else if(linecyc < MCLK_WEIRD_END) { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1637 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1638 { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1639 case 0: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1640 slot = 0; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1641 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1642 case 19: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1643 slot = 1; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1644 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1645 case 39: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1646 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1647 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1648 case 59: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1649 slot = 2; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1650 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1651 case 79: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1652 slot = 3; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1653 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1654 case 97: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1655 slot = 4; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1656 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1657 case 117: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1658 slot = 5; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1659 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1660 case 137: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1661 slot = 6; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1662 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1663 case 157: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1664 slot = 7; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1665 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1666 case 175: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1667 slot = 8; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1668 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1669 case 195: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1670 slot = 9; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1671 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1672 case 215: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1673 slot = 11; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1674 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1675 case 235: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1676 slot = 12; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1677 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1678 case 253: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1679 slot = 13; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1680 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1681 case 273: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1682 slot = 14; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1683 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1684 case 293: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1685 slot = 15; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1686 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1687 case 313: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1688 slot = 16; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1689 break; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1690 default: |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1691 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1692 exit(1); |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1693 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1694 slot += HSYNC_SLOT_H40; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1695 } else { |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1696 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1697 } |
|
671a5be51522
Update hv counter calculation for clock wonkiness
Mike Pavone <pavone@retrodev.com>
parents:
331
diff
changeset
|
1698 linecyc = slot * 2; |
| 137 | 1699 if (linecyc >= 86) { |
| 1700 linecyc -= 86; | |
| 1701 } else { | |
| 1702 linecyc += 334; | |
| 1703 } | |
| 1704 if (linecyc > 0x16C) { | |
| 1705 linecyc += 92; | |
| 1706 } | |
| 1707 } else { | |
| 1708 linecyc /= 10; | |
| 1709 if (linecyc >= 74) { | |
| 1710 linecyc -= 74; | |
| 1711 } else { | |
| 1712 linecyc += 268; | |
| 1713 } | |
| 1714 if (linecyc > 0x127) { | |
| 1715 linecyc += 170; | |
| 1716 } | |
| 1717 } | |
| 1718 linecyc &= 0xFF; | |
|
413
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1719 if (context->double_res) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1720 line <<= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1721 if (line & 0x100) { |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1722 line |= 1; |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1723 } |
|
36fbbced25c2
Initial work on interlace
Mike Pavone <pavone@retrodev.com>
parents:
337
diff
changeset
|
1724 } |
| 137 | 1725 return (line << 8) | linecyc; |
| 1726 } | |
| 1727 | |
|
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1728 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1729 { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1730 context->cycles -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1731 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1732 if (start->cycle >= deduction) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1733 start->cycle -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1734 } else { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1735 start->cycle = 0; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1736 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1737 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1738 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1739 |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1740 uint32_t vdp_next_hint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1741 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1742 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1743 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1744 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1745 if (context->flags2 & FLAG2_HINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1746 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1747 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1748 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1749 uint32_t line = context->cycles / MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1750 if (line >= active_lines) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1751 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1752 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1753 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
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1754 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
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1755 if (!line) { |
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1756 hcycle += MCLKS_LINE; |
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1757 } |
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1758 return hcycle; |
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1759 } |
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1760 |
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1761 uint32_t vdp_next_vint(vdp_context * context) |
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1762 { |
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327
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1763 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
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1764 return 0xFFFFFFFF; |
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1765 } |
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1766 if (context->flags2 & FLAG2_VINT_PENDING) { |
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1767 return context->cycles; |
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1768 } |
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1769 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
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1770 uint32_t vcycle = MCLKS_LINE * active_lines; |
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1771 if (context->latched_mode & BIT_H40) { |
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1772 vcycle += VINT_CYCLE_H40; |
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1773 } else { |
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1774 vcycle += VINT_CYCLE_H32; |
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1775 } |
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1776 if (vcycle < context->cycles) { |
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1777 return 0xFFFFFFFF; |
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1778 } |
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1779 return vcycle; |
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1780 } |
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1781 |
| 333 | 1782 uint32_t vdp_next_vint_z80(vdp_context * context) |
| 1783 { | |
| 1784 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; | |
| 1785 uint32_t vcycle = MCLKS_LINE * active_lines; | |
| 1786 if (context->latched_mode & BIT_H40) { | |
| 1787 vcycle += VINT_CYCLE_H40; | |
| 1788 } else { | |
| 1789 vcycle += VINT_CYCLE_H32; | |
| 1790 } | |
| 1791 return vcycle; | |
| 1792 } | |
| 1793 | |
|
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1794 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
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1795 { |
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1796 if (int_num == 6) { |
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1797 context->flags2 &= ~FLAG2_VINT_PENDING; |
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1798 } else if(int_num ==4) { |
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1799 context->flags2 &= ~FLAG2_HINT_PENDING; |
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1800 } |
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1801 } |
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1802 |