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comparison z80_to_x86.c @ 1050:d06c947a9a77

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Implement undoumented flag bits for DAA, CPL, SCF and CCF
author Michael Pavone <pavone@retrodev.com>
date Thu, 28 Jul 2016 23:37:46 -0700
parents ef7ee9919a73
children 11ff5726fd5e
comparison
equal deleted inserted replaced
1049:ef7ee9919a73 1050:d06c947a9a77
1297 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S)); 1297 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
1298 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV)); 1298 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
1299 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B); 1299 xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
1300 bt_ir(code, 4, opts->gen.scratch1, SZ_B); 1300 bt_ir(code, 4, opts->gen.scratch1, SZ_B);
1301 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H)); 1301 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
1302 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1302 break; 1303 break;
1303 } 1304 }
1304 case Z80_CPL: 1305 case Z80_CPL:
1305 cycles(&opts->gen, num_cycles); 1306 cycles(&opts->gen, num_cycles);
1306 not_r(code, opts->regs[Z80_A], SZ_B); 1307 not_r(code, opts->regs[Z80_A], SZ_B);
1307 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); 1308 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1308 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1309 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1310 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1309 break; 1311 break;
1310 case Z80_NEG: 1312 case Z80_NEG:
1311 cycles(&opts->gen, num_cycles); 1313 cycles(&opts->gen, num_cycles);
1312 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B); 1314 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
1313 neg_r(code, opts->regs[Z80_A], SZ_B); 1315 neg_r(code, opts->regs[Z80_A], SZ_B);
1325 cycles(&opts->gen, num_cycles); 1327 cycles(&opts->gen, num_cycles);
1326 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B); 1328 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
1327 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); 1329 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1328 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1330 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1329 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B); 1331 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1332 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1330 break; 1333 break;
1331 case Z80_SCF: 1334 case Z80_SCF:
1332 cycles(&opts->gen, num_cycles); 1335 cycles(&opts->gen, num_cycles);
1333 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B); 1336 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
1334 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B); 1337 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
1335 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B); 1338 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
1339 mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
1336 break; 1340 break;
1337 case Z80_NOP: 1341 case Z80_NOP:
1338 cycles(&opts->gen, num_cycles); 1342 cycles(&opts->gen, num_cycles);
1339 break; 1343 break;
1340 case Z80_HALT: { 1344 case Z80_HALT: {