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changeset 1050:d06c947a9a77

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Implement undoumented flag bits for DAA, CPL, SCF and CCF
author Michael Pavone <pavone@retrodev.com>
date Thu, 28 Jul 2016 23:37:46 -0700
parents ef7ee9919a73
children 11ff5726fd5e
files z80_to_x86.c
diffstat 1 files changed, 4 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/z80_to_x86.c	Thu Jul 28 22:59:09 2016 -0700
+++ b/z80_to_x86.c	Thu Jul 28 23:37:46 2016 -0700
@@ -1299,6 +1299,7 @@
 		xor_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
 		bt_ir(code, 4, opts->gen.scratch1, SZ_B);
 		setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
+		mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 		break;
 	}
 	case Z80_CPL:
@@ -1306,6 +1307,7 @@
 		not_r(code, opts->regs[Z80_A], SZ_B);
 		mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
 		mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
+		mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 		break;
 	case Z80_NEG:
 		cycles(&opts->gen, num_cycles);
@@ -1327,12 +1329,14 @@
 		xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
+		mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 		break;
 	case Z80_SCF:
 		cycles(&opts->gen, num_cycles);
 		mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
 		mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_H), SZ_B);
+		mov_rrdisp(code, opts->regs[Z80_A], opts->gen.context_reg, zf_off(ZF_XY), SZ_B);
 		break;
 	case Z80_NOP:
 		cycles(&opts->gen, num_cycles);