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comparison gen_x86.c @ 2226:d15c68157288

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Fix implementation ot 68K trapv instruction
author Michael Pavone <pavone@retrodev.com>
date Mon, 05 Sep 2022 12:00:02 -0700
parents e45a317802bd
children
comparison
equal deleted inserted replaced
2225:e22137f0aca4 2226:d15c68157288
1155 void imul_irr(code_info *code, int32_t val, uint8_t src, uint8_t dst, uint8_t size) 1155 void imul_irr(code_info *code, int32_t val, uint8_t src, uint8_t dst, uint8_t size)
1156 { 1156 {
1157 if (size == SZ_B) { 1157 if (size == SZ_B) {
1158 fatal_error("imul immediate only supports 16-bit sizes and up"); 1158 fatal_error("imul immediate only supports 16-bit sizes and up");
1159 } 1159 }
1160 1160
1161 x86_ir(code, OP_IMUL, dst, 0, val, src, size); 1161 x86_ir(code, OP_IMUL, dst, 0, val, src, size);
1162 } 1162 }
1163 1163
1164 void not_r(code_info *code, uint8_t dst, uint8_t size) 1164 void not_r(code_info *code, uint8_t dst, uint8_t size)
1165 { 1165 {
1711 1711
1712 void bit_rr(code_info *code, uint8_t op2, uint8_t src, uint8_t dst, uint8_t size) 1712 void bit_rr(code_info *code, uint8_t op2, uint8_t src, uint8_t dst, uint8_t size)
1713 { 1713 {
1714 check_alloc_code(code, 5); 1714 check_alloc_code(code, 5);
1715 code_ptr out = code->cur; 1715 code_ptr out = code->cur;
1716 if (src >= AH && src <= BH || dst >= AH && dst <= BH) {
1717 fatal_error("attempt to use *H reg in a bit instruction with bit number in register. opcode = %X\n", op2);
1718 }
1716 if (size == SZ_W) { 1719 if (size == SZ_W) {
1717 *(out++) = PRE_SIZE; 1720 *(out++) = PRE_SIZE;
1718 } 1721 }
1719 if (size == SZ_Q || src >= R8 || dst >= R8) { 1722 if (size == SZ_Q || src >= R8 || dst >= R8) {
1720 *out = PRE_REX; 1723 *out = PRE_REX;
1739 1742
1740 void bit_rrdisp(code_info *code, uint8_t op2, uint8_t src, uint8_t dst_base, int32_t dst_disp, uint8_t size) 1743 void bit_rrdisp(code_info *code, uint8_t op2, uint8_t src, uint8_t dst_base, int32_t dst_disp, uint8_t size)
1741 { 1744 {
1742 check_alloc_code(code, 9); 1745 check_alloc_code(code, 9);
1743 code_ptr out = code->cur; 1746 code_ptr out = code->cur;
1747 if (src >= AH && src <= BH) {
1748 fatal_error("attempt to use *H reg in a bit instruction with bit number in register. opcode = %X\n", op2);
1749 }
1744 if (size == SZ_W) { 1750 if (size == SZ_W) {
1745 *(out++) = PRE_SIZE; 1751 *(out++) = PRE_SIZE;
1746 } 1752 }
1747 if (size == SZ_Q || src >= R8 || dst_base >= R8) { 1753 if (size == SZ_Q || src >= R8 || dst_base >= R8) {
1748 *out = PRE_REX; 1754 *out = PRE_REX;
1776 1782
1777 void bit_ir(code_info *code, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size) 1783 void bit_ir(code_info *code, uint8_t op_ex, uint8_t val, uint8_t dst, uint8_t size)
1778 { 1784 {
1779 check_alloc_code(code, 6); 1785 check_alloc_code(code, 6);
1780 code_ptr out = code->cur; 1786 code_ptr out = code->cur;
1787 if (dst >= AH && dst <= BH) {
1788 //bit instructions are never 8-bit so we can't directly specify the high byte regs
1789 //but we can simulate that by adjusting the bit we're testing
1790 dst -= AH;
1791 val += 8;
1792 }
1781 if (size == SZ_W) { 1793 if (size == SZ_W) {
1782 *(out++) = PRE_SIZE; 1794 *(out++) = PRE_SIZE;
1783 } 1795 }
1784 if (size == SZ_Q || dst >= R8) { 1796 if (size == SZ_Q || dst >= R8) {
1785 *out = PRE_REX; 1797 *out = PRE_REX;
2161 #if defined(X86_64) && defined(_WIN32) 2173 #if defined(X86_64) && defined(_WIN32)
2162 sub_ir(code, 32, RSP, SZ_PTR); 2174 sub_ir(code, 32, RSP, SZ_PTR);
2163 code->stack_off += 32; 2175 code->stack_off += 32;
2164 adjust += 32; 2176 adjust += 32;
2165 #endif 2177 #endif
2166 2178
2167 return stack_args * sizeof(void *) + adjust; 2179 return stack_args * sizeof(void *) + adjust;
2168 } 2180 }
2169 2181
2170 void call_args(code_info *code, code_ptr fun, uint32_t num_args, ...) 2182 void call_args(code_info *code, code_ptr fun, uint32_t num_args, ...)
2171 { 2183 {