--- a/gen_x86.c	Mon Sep 05 01:15:15 2022 -0700
+++ b/gen_x86.c	Mon Sep 05 12:00:02 2022 -0700
@@ -1157,7 +1157,7 @@
 	if (size == SZ_B) {
 		fatal_error("imul immediate only supports 16-bit sizes and up");
 	}
-	
+
 	x86_ir(code, OP_IMUL, dst, 0, val, src, size);
 }
 
@@ -1713,6 +1713,9 @@
 {
 	check_alloc_code(code, 5);
 	code_ptr out = code->cur;
+	if (src >= AH && src <= BH || dst >= AH && dst <= BH) {
+		fatal_error("attempt to use *H reg in a bit instruction with bit number in register. opcode = %X\n", op2);
+	}
 	if (size == SZ_W) {
 		*(out++) = PRE_SIZE;
 	}
@@ -1741,6 +1744,9 @@
 {
 	check_alloc_code(code, 9);
 	code_ptr out = code->cur;
+	if (src >= AH && src <= BH) {
+		fatal_error("attempt to use *H reg in a bit instruction with bit number in register. opcode = %X\n", op2);
+	}
 	if (size == SZ_W) {
 		*(out++) = PRE_SIZE;
 	}
@@ -1778,6 +1784,12 @@
 {
 	check_alloc_code(code, 6);
 	code_ptr out = code->cur;
+	if (dst >= AH && dst <= BH) {
+		//bit instructions are never 8-bit so we can't directly specify the high byte regs
+		//but we can simulate that by adjusting the bit we're testing
+		dst -= AH;
+		val += 8;
+	}
 	if (size == SZ_W) {
 		*(out++) = PRE_SIZE;
 	}
@@ -2163,7 +2175,7 @@
 	code->stack_off += 32;
 	adjust += 32;
 #endif
-	
+
 	return stack_args * sizeof(void *) + adjust;
 }
 

--- a/m68k_core_x86.c	Mon Sep 05 01:15:15 2022 -0700
+++ b/m68k_core_x86.c	Mon Sep 05 12:00:02 2022 -0700
@@ -2393,7 +2393,6 @@
 void translate_m68k_trapv(m68k_options *opts, m68kinst *inst)
 {
 	code_info *code = &opts->gen.code;
-	cycles(&opts->gen, BUS);
 	flag_to_carry(opts, FLAG_V);
 	code_ptr no_trap = code->cur + 1;
 	jcc(code, CC_NC, no_trap);
@@ -2401,6 +2400,7 @@
 	ldi_native(opts, inst->address+2, opts->gen.scratch1);
 	jmp(code, opts->trap);
 	*no_trap = code->cur - (no_trap + 1);
+	cycles(&opts->gen, BUS);
 }
 
 void translate_m68k_odd(m68k_options *opts, m68kinst *inst)