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Implement VDP read latency and invalid write delays revealed by Ti_'s instruction timing ROM
author Michael Pavone <pavone@retrodev.com>
date Mon, 05 Sep 2022 22:18:25 -0700
parents 1cccc57c069a
children c149c929361c
comparison
equal deleted inserted replaced
2226:d15c68157288 2227:eaaf28af3c94
203 //cycle count in MCLKs 203 //cycle count in MCLKs
204 uint32_t cycles; 204 uint32_t cycles;
205 uint32_t pending_vint_start; 205 uint32_t pending_vint_start;
206 uint32_t pending_hint_start; 206 uint32_t pending_hint_start;
207 uint32_t top_offset; 207 uint32_t top_offset;
208 uint32_t read_latency;
208 uint16_t vsram[MAX_VSRAM_SIZE]; 209 uint16_t vsram[MAX_VSRAM_SIZE];
209 uint16_t vscroll_latch[2]; 210 uint16_t vscroll_latch[2];
210 uint16_t vcounter; 211 uint16_t vcounter;
211 uint16_t inactive_start; 212 uint16_t inactive_start;
212 uint16_t border_top; 213 uint16_t border_top;
268 uint32_t vdp_run_to_vblank(vdp_context * context); 269 uint32_t vdp_run_to_vblank(vdp_context * context);
269 //runs until the target cycle is reached or the current DMA operation has completed, whicever comes first 270 //runs until the target cycle is reached or the current DMA operation has completed, whicever comes first
270 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles); 271 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles);
271 uint8_t vdp_load_gst(vdp_context * context, FILE * state_file); 272 uint8_t vdp_load_gst(vdp_context * context, FILE * state_file);
272 uint8_t vdp_save_gst(vdp_context * context, FILE * outfile); 273 uint8_t vdp_save_gst(vdp_context * context, FILE * outfile);
273 int vdp_control_port_write(vdp_context * context, uint16_t value); 274 int vdp_control_port_write(vdp_context * context, uint16_t value, uint32_t cpu_cycle);
274 void vdp_control_port_write_pbc(vdp_context * context, uint8_t value); 275 void vdp_control_port_write_pbc(vdp_context * context, uint8_t value);
275 int vdp_data_port_write(vdp_context * context, uint16_t value); 276 int vdp_data_port_write(vdp_context * context, uint16_t value);
276 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value); 277 void vdp_data_port_write_pbc(vdp_context * context, uint8_t value);
277 void vdp_test_port_write(vdp_context * context, uint16_t value); 278 void vdp_test_port_write(vdp_context * context, uint16_t value);
278 uint16_t vdp_control_port_read(vdp_context * context); 279 uint16_t vdp_control_port_read(vdp_context * context);
279 uint16_t vdp_data_port_read(vdp_context * context); 280 uint16_t vdp_data_port_read(vdp_context * context, uint32_t *cpu_cycle, uint32_t cpu_divider);
280 uint8_t vdp_data_port_read_pbc(vdp_context * context); 281 uint8_t vdp_data_port_read_pbc(vdp_context * context);
281 void vdp_latch_hv(vdp_context *context); 282 void vdp_latch_hv(vdp_context *context);
282 uint16_t vdp_hv_counter_read(vdp_context * context); 283 uint16_t vdp_hv_counter_read(vdp_context * context);
283 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction); 284 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction);
284 uint32_t vdp_next_hint(vdp_context * context); 285 uint32_t vdp_next_hint(vdp_context * context);