Mercurial > repos > blastem
diff vdp.h @ 2227:eaaf28af3c94
Implement VDP read latency and invalid write delays revealed by Ti_'s instruction timing ROM
| author | Michael Pavone <pavone@retrodev.com> |
|---|---|
| date | Mon, 05 Sep 2022 22:18:25 -0700 |
| parents | 1cccc57c069a |
| children | c149c929361c |
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--- a/vdp.h Mon Sep 05 12:00:02 2022 -0700 +++ b/vdp.h Mon Sep 05 22:18:25 2022 -0700 @@ -205,6 +205,7 @@ uint32_t pending_vint_start; uint32_t pending_hint_start; uint32_t top_offset; + uint32_t read_latency; uint16_t vsram[MAX_VSRAM_SIZE]; uint16_t vscroll_latch[2]; uint16_t vcounter; @@ -270,13 +271,13 @@ void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles); uint8_t vdp_load_gst(vdp_context * context, FILE * state_file); uint8_t vdp_save_gst(vdp_context * context, FILE * outfile); -int vdp_control_port_write(vdp_context * context, uint16_t value); +int vdp_control_port_write(vdp_context * context, uint16_t value, uint32_t cpu_cycle); void vdp_control_port_write_pbc(vdp_context * context, uint8_t value); int vdp_data_port_write(vdp_context * context, uint16_t value); void vdp_data_port_write_pbc(vdp_context * context, uint8_t value); void vdp_test_port_write(vdp_context * context, uint16_t value); uint16_t vdp_control_port_read(vdp_context * context); -uint16_t vdp_data_port_read(vdp_context * context); +uint16_t vdp_data_port_read(vdp_context * context, uint32_t *cpu_cycle, uint32_t cpu_divider); uint8_t vdp_data_port_read_pbc(vdp_context * context); void vdp_latch_hv(vdp_context *context); uint16_t vdp_hv_counter_read(vdp_context * context);