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log m68k_to_x86.c @ 290:171f97e70d85

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age author description
Thu, 25 Apr 2013 21:01:11 -0700 Mike Pavone Get Z80 core working for simple programs
Sun, 21 Apr 2013 16:44:46 -0700 Mike Pavone Fix overflow detection in divs. Fix negative immediate source for divs
Sun, 21 Apr 2013 13:00:34 -0700 Mike Pavone Implement CHK instruction (not fully tested).
Sun, 21 Apr 2013 11:42:45 -0700 Mike Pavone Fixed a couple bugs in roxl/roxr. X flag wasn't being saved properly and rotates of more than 31 bits were messed up as the X flag was being thrown away between the first 31 bits of rotate and the rest.
Sat, 20 Apr 2013 17:41:07 -0700 Mike Pavone Fix muls with a negative immediate source.
Sat, 20 Apr 2013 16:53:01 -0700 Mike Pavone Fix modulo on bit operations with a memory destination
Sat, 20 Apr 2013 14:36:41 -0700 Mike Pavone Fix overflow flag behavior for lsl/lsr/asr
Sat, 20 Apr 2013 00:36:50 -0700 Mike Pavone Fix autoincrement on a7 when used as a destination in a byte sized instruction
Fri, 19 Apr 2013 21:36:54 -0700 Mike Pavone Fix some bugs related to sign-extension of address registers and pre-decrement amount for a7 when used as a source.
Tue, 16 Apr 2013 22:29:00 -0700 Mike Pavone Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Tue, 16 Apr 2013 09:31:21 -0700 Mike Pavone Small bit of cleanup
Sun, 27 Jan 2013 13:07:26 -0800 Mike Pavone Fix movem reg to mem for certain addressing modes
Sat, 26 Jan 2013 02:47:26 -0800 Mike Pavone Flag fixes for div, negx and not
Sat, 26 Jan 2013 01:33:32 -0800 Mike Pavone Tweaks to make blastem compatible with m68k-tester
Fri, 25 Jan 2013 18:39:22 -0800 Mike Pavone Fix overflow flag on ASL
Thu, 17 Jan 2013 20:00:07 -0800 Mike Pavone Add instruction address logging to translator and support for reading an address log to the disassembler
Thu, 17 Jan 2013 08:19:29 -0800 Mike Pavone Implement pc indexed mode as move dst
Wed, 16 Jan 2013 22:40:56 -0800 Mike Pavone Implement ABCD an SBCD. Fix BTEST with register source.
Tue, 15 Jan 2013 00:14:36 -0800 Mike Pavone Implement support for self-modifying code
Mon, 14 Jan 2013 21:56:54 -0800 Mike Pavone Prep work for handling games that modify code in RAM
Sun, 13 Jan 2013 23:48:04 -0800 Mike Pavone Fix movem.w when dest is register list
Sun, 13 Jan 2013 23:06:26 -0800 Mike Pavone Fix return address for areg displacement mode JSR
Sun, 13 Jan 2013 13:01:13 -0800 Mike Pavone Fix a bunch of bugs in the CPU core, add a 68K debugger
Wed, 09 Jan 2013 22:31:07 -0800 Mike Pavone Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Wed, 09 Jan 2013 21:41:55 -0800 Mike Pavone Fix -(a7) dest when size is byte
Wed, 09 Jan 2013 21:08:37 -0800 Mike Pavone Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Tue, 08 Jan 2013 09:34:24 -0800 Mike Pavone Fix scc to set reg to 0xFF rather than 1 when the condition is true
Sun, 06 Jan 2013 22:45:45 -0800 Mike Pavone Fix order of reading saved pc and swapping user and system stack pointers
Sun, 06 Jan 2013 21:44:54 -0800 Mike Pavone Make sure we bail out of translation after translating an invalid instruction
Sun, 06 Jan 2013 21:42:57 -0800 Mike Pavone Print a message when we try to run an invalid instruction, not when we try to translate it
Sun, 06 Jan 2013 20:49:42 -0800 Mike Pavone Fix order of SR and PC saved in an exception stack frame
Sun, 06 Jan 2013 18:31:17 -0800 Mike Pavone Implement areg displacement mode for jsr
Sun, 06 Jan 2013 15:20:23 -0800 Mike Pavone Implement negx
Sun, 06 Jan 2013 14:41:26 -0800 Mike Pavone Implement movep
Sun, 06 Jan 2013 14:00:45 -0800 Mike Pavone Implement EORI CCR/SR
Sun, 06 Jan 2013 13:58:33 -0800 Mike Pavone Implement RTR
Sun, 06 Jan 2013 13:42:13 -0800 Mike Pavone Fix a bunch of addressing modes in movem when a register list is the destination
Sun, 06 Jan 2013 12:17:10 -0800 Mike Pavone Minor optimization and a cycle count fix to lea
Sun, 06 Jan 2013 10:54:45 -0800 Mike Pavone Initialize status register to proper value on startup
Sat, 05 Jan 2013 22:59:51 -0800 Mike Pavone Fix certain address modes with lea when the destination is not a native register
Sat, 05 Jan 2013 02:18:31 -0800 Mike Pavone Implement more movem modes src
Sat, 05 Jan 2013 01:55:11 -0800 Mike Pavone Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst
Sat, 05 Jan 2013 01:31:28 -0800 Mike Pavone FIx movem when src is reg list and dst is not a areg predec mode
Sat, 05 Jan 2013 00:53:50 -0800 Mike Pavone Fix predec address mode when used as source
Fri, 04 Jan 2013 23:52:20 -0800 Mike Pavone Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
Fri, 04 Jan 2013 23:25:23 -0800 Mike Pavone Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive)
Fri, 04 Jan 2013 23:21:07 -0800 Mike Pavone Don't use the native call stack for M68K calls by default
Fri, 04 Jan 2013 22:51:01 -0800 Mike Pavone Small fix for bit instructions
Thu, 03 Jan 2013 22:49:21 -0800 Mike Pavone Implement TRAP (untested)
Thu, 03 Jan 2013 22:07:40 -0800 Mike Pavone Implement MULU/MULS and DIVU/DIVS
Tue, 01 Jan 2013 09:40:17 -0800 Mike Pavone Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mon, 31 Dec 2012 20:09:09 -0800 Mike Pavone Implement most of the "X" instructions
Sun, 30 Dec 2012 09:55:07 -0800 Mike Pavone Add support for pc indexed addressing mode to lea
Sun, 30 Dec 2012 07:52:44 -0800 Mike Pavone Support more address modes for jmp
Sat, 29 Dec 2012 23:40:30 -0800 Mike Pavone Fix swap
Sat, 29 Dec 2012 23:08:14 -0800 Mike Pavone Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Sat, 29 Dec 2012 22:22:53 -0800 Mike Pavone Fix check in translate_m68k_src that deals with instructions for which both operands are registers that are not mapped to a native x86-64 register
Sat, 29 Dec 2012 22:11:28 -0800 Mike Pavone Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
Sat, 29 Dec 2012 21:55:42 -0800 Mike Pavone Some fixes for translating code in located in RAM
Sat, 29 Dec 2012 21:10:07 -0800 Mike Pavone Implement the rest of the bit instructions
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