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changeset 157:301470eb870b

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Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction.
author Mike Pavone <pavone@retrodev.com>
date Fri, 04 Jan 2013 23:52:20 -0800
parents 3900cfde9dbb
children a2ab895d9708
files m68k_to_x86.c
diffstat 1 files changed, 20 insertions(+), 20 deletions(-) [+]
line wrap: on
line diff
--- a/m68k_to_x86.c	Fri Jan 04 23:25:23 2013 -0800
+++ b/m68k_to_x86.c	Fri Jan 04 23:52:20 2013 -0800
@@ -2793,7 +2793,7 @@
 				}
 				dst = and_ir(dst, 63, SCRATCH1, SZ_D);
 				zero_off = dst+1;
-				dst = jcc(dst, CC_NZ, dst+2);
+				dst = jcc(dst, CC_Z, dst+2);
 				dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
 				dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
 				dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
@@ -2855,9 +2855,9 @@
 			//Memory rotate
 			dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
 			if (inst->op == M68K_ROXL) {
-				dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
+				dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
 			} else {
-				dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
+				dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
 			}
 			dst = setcc_r(dst, CC_C, FLAG_C);
 			dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
@@ -2870,15 +2870,15 @@
 				dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
 				if (dst_op.mode == MODE_REG_DIRECT) {
 					if (inst->op == M68K_ROXL) {
-						dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
+						dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
 					} else {
-						dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
+						dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
 					}
 				} else {
 					if (inst->op == M68K_ROXL) {
-						dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
 					} else {
-						dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
 					}
 				}
 				dst = setcc_r(dst, CC_C, FLAG_C);
@@ -2892,7 +2892,7 @@
 				}
 				dst = and_ir(dst, 63, SCRATCH1, SZ_D);
 				zero_off = dst+1;
-				dst = jcc(dst, CC_NZ, dst+2);
+				dst = jcc(dst, CC_Z, dst+2);
 				dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
 				dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
 				dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
@@ -2901,19 +2901,19 @@
 				dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
 				if (dst_op.mode == MODE_REG_DIRECT) {
 					if (inst->op == M68K_ROXL) {
-						dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
-						dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
+						dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size);
+						dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
 					} else {
-						dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
-						dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
+						dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size);
+						dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
 					}
 				} else {
 					if (inst->op == M68K_ROXL) {
-						dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
-						dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
 					} else {
-						dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
-						dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
 					}
 				}
 				dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
@@ -2921,15 +2921,15 @@
 				dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
 				if (dst_op.mode == MODE_REG_DIRECT) {
 					if (inst->op == M68K_ROXL) {
-						dst = rol_clr(dst, dst_op.base, inst->extra.size);
+						dst = rcl_clr(dst, dst_op.base, inst->extra.size);
 					} else {
-						dst = ror_clr(dst, dst_op.base, inst->extra.size);
+						dst = rcr_clr(dst, dst_op.base, inst->extra.size);
 					}
 				} else {
 					if (inst->op == M68K_ROXL) {
-						dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
 					} else {
-						dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
+						dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
 					}
 				}
 				dst = setcc_r(dst, CC_C, FLAG_C);