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log cpu_dsl.py @ 2666:38c281ef57b0

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age author description
Fri, 07 Mar 2025 23:40:58 -0800 Michael Pavone Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Mon, 24 Feb 2025 23:38:32 -0800 Michael Pavone Fix flags for mulu/muls in new 68K core
Sat, 22 Feb 2025 01:31:51 -0800 Michael Pavone Fix V flag for asl in new CPU core
Fri, 21 Feb 2025 01:45:04 -0800 Michael Pavone Implement stop in new 68K core
Mon, 17 Feb 2025 23:40:36 -0800 Michael Pavone Fix some issues with constant folding in CPU DSL
Sat, 15 Feb 2025 23:06:49 -0800 Michael Pavone Fix asr and lsr in new 68K core
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