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log cpu_dsl.py @ 1742:6290c88949bd

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Mon, 04 Feb 2019 23:46:35 -0800 Michael Pavone Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Mon, 04 Feb 2019 22:20:51 -0800 Michael Pavone Implement DD/FD prefixes for instructions that don't reference HL
Mon, 04 Feb 2019 21:43:43 -0800 Michael Pavone Fixed some issues involving conditional execution and temporaries/constant folding
Sun, 03 Feb 2019 11:05:40 -0800 Michael Pavone Get new Z80 core running in CPM harness
Sun, 03 Feb 2019 10:40:41 -0800 Michael Pavone Implemented the rest of the block move instructions in new Z80 core
Sat, 02 Feb 2019 23:02:19 -0800 Michael Pavone Implemented LDI in new Z80 core
Sat, 02 Feb 2019 15:35:15 -0800 Michael Pavone Implemented RES instruction in new Z80 core
Fri, 01 Feb 2019 22:16:56 -0800 Michael Pavone Miscellaneous small fixes to new Z80 core
Thu, 31 Jan 2019 23:33:36 -0800 Michael Pavone Implemented shift instructions in new Z80 core
Thu, 31 Jan 2019 23:03:51 -0800 Michael Pavone Implemented the rest of the rotate instructions in new Z80 core
Thu, 31 Jan 2019 22:41:37 -0800 Michael Pavone Implementation of some of the rotate instructions in new Z80 core
Wed, 30 Jan 2019 21:47:35 -0800 Michael Pavone Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Wed, 30 Jan 2019 09:32:01 -0800 Michael Pavone Better error reporting when an instruction is given an insufficient number of parameters
Tue, 29 Jan 2019 23:56:48 -0800 Michael Pavone Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Tue, 29 Jan 2019 22:16:57 -0800 Michael Pavone Implement parity flag calculation type
Tue, 29 Jan 2019 21:26:39 -0800 Michael Pavone Actually correct overflow flag calculation in CPU DSL
Mon, 28 Jan 2019 22:56:43 -0800 Michael Pavone Fix sbc and implement carry/overflow flags for it in CPU DSL
Mon, 28 Jan 2019 22:49:02 -0800 Michael Pavone Implementation of carry/overflow flags for adc instructions in CPU DSL
Mon, 28 Jan 2019 22:37:46 -0800 Michael Pavone Fixed flag calculation for sub instructions in CPU DSL
Mon, 28 Jan 2019 21:30:23 -0800 Michael Pavone Less broken flag calulcation for sub instructions in CPU DSL
Mon, 28 Jan 2019 21:15:27 -0800 Michael Pavone Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction
Mon, 28 Jan 2019 20:54:55 -0800 Michael Pavone First stab at carry and half-carry calculation in CPU DSL
Mon, 28 Jan 2019 19:24:04 -0800 Michael Pavone Fix zero flag calculation in CPU DSL
Sun, 27 Jan 2019 14:37:37 -0800 Michael Pavone Implemented sbc instruction in CPU DSL
Sun, 27 Jan 2019 05:55:08 -0800 Michael Pavone Added adc instruction to CPU DSL
Fri, 25 Jan 2019 14:30:55 -0800 Michael Pavone Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Fri, 25 Jan 2019 14:13:46 -0800 Michael Pavone Fix constant propagation to a non-ephemeral destination in CPU DSL
Fri, 25 Jan 2019 13:55:30 -0800 Michael Pavone Fixed missing semicolon in coalesceFlags
Fri, 25 Jan 2019 13:45:58 -0800 Michael Pavone Added new sext instruction for sign extension to CPU sdl
Sat, 06 Oct 2018 17:33:15 -0700 Michael Pavone Implement program ROM reads
Thu, 04 Oct 2018 19:12:56 -0700 Michael Pavone Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Mon, 01 Oct 2018 19:16:54 -0700 Michael Pavone Clean up warnings from -1 case
Mon, 01 Oct 2018 19:11:17 -0700 Michael Pavone Getting SVP core closer to compiling
Tue, 25 Sep 2018 09:33:46 -0700 Michael Pavone Fix implementation cmp+condition version of if in CPU DSL
Mon, 24 Sep 2018 19:09:16 -0700 Michael Pavone Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Fri, 21 Sep 2018 09:26:12 -0700 Michael Pavone Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
Tue, 18 Sep 2018 09:06:42 -0700 Michael Pavone Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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