--- a/cpu_dsl.py	Thu Oct 04 19:12:56 2018 -0700
+++ b/cpu_dsl.py	Sat Oct 06 17:33:15 2018 -0700
@@ -676,11 +676,15 @@
 class Registers:
 	def __init__(self):
 		self.regs = {}
+		self.pointers = {}
 		self.regArrays = {}
 		self.regToArray = {}
 	
 	def addReg(self, name, size):
 		self.regs[name] = size
+		
+	def addPointer(self, name, size):
+		self.pointers[name] = size
 	
 	def addRegArray(self, name, size, regs):
 		self.regArrays[name] = (size, regs)
@@ -721,11 +725,16 @@
 		elif len(parts) > 2:
 			self.addRegArray(parts[0], int(parts[1]), parts[2:])
 		else:
-			self.addReg(parts[0], int(parts[1]))
+			if parts[1].startswith('ptr'):
+				self.addPointer(parts[0], int(parts[1][3:]))
+			else:
+				self.addReg(parts[0], int(parts[1]))
 		return self
 
 	def writeHeader(self, otype, hFile):
 		fieldList = []
+		for pointer in self.pointers:
+			hFile.write('\n\tuint{sz}_t *{nm};'.format(nm=pointer, sz=self.pointers[pointer]))
 		for reg in self.regs:
 			if not self.isRegArrayMember(reg):
 				fieldList.append((self.regs[reg], 1, reg))

--- a/svp.cpu	Thu Oct 04 19:12:56 2018 -0700
+++ b/svp.cpu	Sat Oct 06 17:33:15 2018 -0700
@@ -6,8 +6,10 @@
 	include svp_util.c
 	
 regs
-	internal 16 scratch1 x y scratch2 st pad pc
+	internal 16 scratch2 x y pad0 st pad1 pc
 	a 32
+	scratch1 32
+	rom ptr16
 	stack 16 stack0 stack1 stack2 stack3 stack4 stack5
 	stackidx 8
 	p 32
@@ -622,7 +624,7 @@
 	
 	if >=U
 	add src src scratch1
-	ocall read_16
+	ocall prog_read_16
 	
 	else
 	mov iram.src scratch1

--- a/svp_util.c	Thu Oct 04 19:12:56 2018 -0700
+++ b/svp_util.c	Sat Oct 06 17:33:15 2018 -0700
@@ -1,5 +1,6 @@
 
-void svp_read_16(svp_context *context)
+void svp_prog_read_16(svp_context *context)
 {
-	context->internal[0] = 0;
+	uint16_t address = context->scratch1 >> 1;
+	context->scratch1 = context->rom[address];
 }