log m68k_to_x86.c @ 151:6b593ea0ed90

age author description
Thu, 03 Jan 2013 22:07:40 -0800 Mike Pavone Implement MULU/MULS and DIVU/DIVS
Tue, 01 Jan 2013 09:40:17 -0800 Mike Pavone Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed.
Mon, 31 Dec 2012 20:09:09 -0800 Mike Pavone Implement most of the "X" instructions
Sun, 30 Dec 2012 09:55:07 -0800 Mike Pavone Add support for pc indexed addressing mode to lea
Sun, 30 Dec 2012 07:52:44 -0800 Mike Pavone Support more address modes for jmp
Sat, 29 Dec 2012 23:40:30 -0800 Mike Pavone Fix swap
Sat, 29 Dec 2012 23:08:14 -0800 Mike Pavone Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed
Sat, 29 Dec 2012 22:22:53 -0800 Mike Pavone Fix check in translate_m68k_src that deals with instructions for which both operands are registers that are not mapped to a native x86-64 register
Sat, 29 Dec 2012 22:11:28 -0800 Mike Pavone Fix encoding of movsx instruction when used with new (i.e. r9-r15) registers. This fixes the indexed addressing modes when used with a word-wide index register
Sat, 29 Dec 2012 21:55:42 -0800 Mike Pavone Some fixes for translating code in located in RAM
Sat, 29 Dec 2012 21:10:07 -0800 Mike Pavone Implement the rest of the bit instructions
Sat, 29 Dec 2012 20:33:39 -0800 Mike Pavone Implemented ROL and ROR
Sat, 29 Dec 2012 12:52:19 -0800 Mike Pavone Fix logic for switching between USP and SSP
Fri, 28 Dec 2012 22:47:10 -0800 Mike Pavone Fix return address pushed to stack for jsr
Fri, 28 Dec 2012 21:36:22 -0800 Mike Pavone cycles should return dst
Fri, 28 Dec 2012 21:20:14 -0800 Mike Pavone Implement pea (untested).
Fri, 28 Dec 2012 17:59:41 -0800 Mike Pavone Defer the correct address for pc relative jsr/jmp
Fri, 28 Dec 2012 17:57:43 -0800 Mike Pavone Implement scc (untested)
Fri, 28 Dec 2012 15:16:36 -0800 Mike Pavone Implement more address modes for jsr
Fri, 28 Dec 2012 14:30:25 -0800 Mike Pavone Fix areg indexed mode for move dst
Fri, 28 Dec 2012 11:07:13 -0800 Mike Pavone Implement ORI to CCR/SR
Fri, 28 Dec 2012 10:37:09 -0800 Mike Pavone Implemented move from SR
Thu, 27 Dec 2012 23:00:11 -0800 Mike Pavone Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp
Thu, 27 Dec 2012 22:41:28 -0800 Mike Pavone allocate a new native code chunk when we run out of space
Thu, 27 Dec 2012 22:11:26 -0800 Mike Pavone Implement areg indexed mode for lea
Thu, 27 Dec 2012 22:05:22 -0800 Mike Pavone Allow use of indexed modes as move dst
Thu, 27 Dec 2012 21:54:54 -0800 Mike Pavone Allow indexed modes to be used as a destination
Thu, 27 Dec 2012 21:32:00 -0800 Mike Pavone Fix address register indexed addressing (probably)
Thu, 27 Dec 2012 21:23:55 -0800 Mike Pavone Fix pc indexed addressing (probably) when used as a source
Thu, 27 Dec 2012 21:19:58 -0800 Mike Pavone Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Thu, 27 Dec 2012 18:21:10 -0800 Mike Pavone Implement EXT, add some fixes to LINK/UNLK
Thu, 27 Dec 2012 10:40:03 -0800 Mike Pavone Fix some bugs in emulation of CLR
Wed, 26 Dec 2012 20:18:58 -0800 Mike Pavone vertical interrupts now work
Wed, 26 Dec 2012 18:20:23 -0800 Mike Pavone RTE doesn't crash the emulator anymore
Wed, 26 Dec 2012 11:09:04 -0800 Mike Pavone Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested).
Sat, 22 Dec 2012 21:37:25 -0800 Mike Pavone Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode
Fri, 21 Dec 2012 21:53:05 -0800 Mike Pavone Added untested support for LINK and UNLK
Fri, 21 Dec 2012 21:26:16 -0800 Mike Pavone Removed some old debug printfs
Fri, 21 Dec 2012 21:19:03 -0800 Mike Pavone Implement JSR for some addressing modes
Fri, 21 Dec 2012 16:38:40 -0800 Mike Pavone Fix some bugs in movem with a register list destination
Fri, 21 Dec 2012 16:04:41 -0800 Mike Pavone Implement a couple of supervisor instructions
Fri, 21 Dec 2012 01:00:52 -0800 Mike Pavone Implement more instructions and address modes
Thu, 20 Dec 2012 09:17:31 -0800 Mike Pavone Make the translator bail out if it hits an instruction I haven't implemented yet
Thu, 20 Dec 2012 00:56:33 -0800 Mike Pavone Fix BTST
Thu, 20 Dec 2012 00:44:59 -0800 Mike Pavone Gamepad support
Wed, 19 Dec 2012 21:25:39 -0800 Mike Pavone Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults
Wed, 19 Dec 2012 20:23:59 -0800 Mike Pavone Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Tue, 18 Dec 2012 22:56:04 -0800 Mike Pavone ecx was getting clobbered before the relevant temp value was used in some cases during memory reads
Tue, 18 Dec 2012 02:16:42 -0800 Mike Pavone Get Flavio's color bar demo kind of sort of working
Sun, 16 Dec 2012 22:25:29 -0800 Mike Pavone Add preliminary support for JMP
Sun, 16 Dec 2012 21:57:52 -0800 Mike Pavone Implement CLR, minor refactor of register offset calculation in context struct
Sat, 15 Dec 2012 23:01:32 -0800 Mike Pavone Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Wed, 12 Dec 2012 23:21:11 -0800 Mike Pavone Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations
Wed, 12 Dec 2012 20:18:06 -0800 Mike Pavone Add support for dbcc instruction
Tue, 04 Dec 2012 19:25:54 -0800 Mike Pavone Initial support for M68k reset vector, rather than starting at an arbitrary address
Tue, 04 Dec 2012 19:13:12 -0800 Mike Pavone M68K to x86 translation works for a limited subset of instructions and addressing modes
Tue, 27 Nov 2012 09:28:13 -0800 Mike Pavone x86 code gen, initial work on translator