| Mon, 05 Sep 2022 12:00:02 -0700 |
Michael Pavone |
Fix implementation ot 68K trapv instruction
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| Mon, 05 Sep 2022 01:15:15 -0700 |
Michael Pavone |
Fix some 68K exception processing cycle times
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| Mon, 05 Sep 2022 00:49:03 -0700 |
Michael Pavone |
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
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| Fri, 11 Feb 2022 22:55:01 -0800 |
Michael Pavone |
Fix regression in booting games with Japanese Mega CD BIOS
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| Wed, 09 Feb 2022 23:39:33 -0800 |
Michael Pavone |
Fix handling of address error for 32-bit accesses
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| Sat, 05 Feb 2022 16:41:01 -0800 |
Michael Pavone |
Fix instruction retranslation for write protectable region of SCD Program RAM
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| Tue, 18 Jan 2022 00:03:50 -0800 |
Michael Pavone |
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
segacd
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| Wed, 10 Jun 2020 19:08:41 -0700 |
Michael Pavone |
Fix cycle timing of a number of 68K instructions
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| Sat, 25 Apr 2020 18:10:40 -0700 |
Michael Pavone |
Fix instruction timing for addq.w #i, (ay) in dynarec
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| Sun, 07 Apr 2019 00:06:29 -0700 |
Michael Pavone |
Get 64-bit builds working for Windows target
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| Fri, 18 May 2018 19:00:10 -0700 |
Michael Pavone |
Fix cycle counts for BCD instructions, RESET, and MOVE from SR
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| Thu, 17 May 2018 00:43:16 -0700 |
Michael Pavone |
Fix instruction timing for a number of instructions with only a single operand
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| Wed, 03 Jan 2018 07:09:39 -0800 |
Michael Pavone |
Fix silly bug in STOP implementation that caused excessive CPU usage
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| Wed, 13 Sep 2017 21:13:11 -0700 |
Michael Pavone |
Push correct PC onto stack on divide by zero for pc-relative case
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