| Mon, 05 Sep 2022 12:00:02 -0700 |
Michael Pavone |
Fix implementation ot 68K trapv instruction
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| Mon, 05 Sep 2022 01:15:15 -0700 |
Michael Pavone |
Fix some 68K exception processing cycle times
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| Mon, 05 Sep 2022 00:49:03 -0700 |
Michael Pavone |
Fix bad 68K instruction timings revealed by Ti_'s test ROM, except those that involve exception timing
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| Fri, 11 Feb 2022 22:55:01 -0800 |
Michael Pavone |
Fix regression in booting games with Japanese Mega CD BIOS
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| Wed, 09 Feb 2022 23:39:33 -0800 |
Michael Pavone |
Fix handling of address error for 32-bit accesses
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| Sat, 05 Feb 2022 16:41:01 -0800 |
Michael Pavone |
Fix instruction retranslation for write protectable region of SCD Program RAM
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| Tue, 18 Jan 2022 00:03:50 -0800 |
Michael Pavone |
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
segacd
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| Wed, 10 Jun 2020 19:08:41 -0700 |
Michael Pavone |
Fix cycle timing of a number of 68K instructions
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| Sat, 25 Apr 2020 18:10:40 -0700 |
Michael Pavone |
Fix instruction timing for addq.w #i, (ay) in dynarec
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| Sun, 07 Apr 2019 00:06:29 -0700 |
Michael Pavone |
Get 64-bit builds working for Windows target
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| Fri, 18 May 2018 19:00:10 -0700 |
Michael Pavone |
Fix cycle counts for BCD instructions, RESET, and MOVE from SR
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| Thu, 17 May 2018 00:43:16 -0700 |
Michael Pavone |
Fix instruction timing for a number of instructions with only a single operand
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| Wed, 03 Jan 2018 07:09:39 -0800 |
Michael Pavone |
Fix silly bug in STOP implementation that caused excessive CPU usage
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| Wed, 13 Sep 2017 21:13:11 -0700 |
Michael Pavone |
Push correct PC onto stack on divide by zero for pc-relative case
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| Wed, 13 Sep 2017 21:06:25 -0700 |
Michael Pavone |
Preserve original address when retranslating instructions instead of switching to the lowest alias
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| Wed, 06 Sep 2017 23:10:11 -0700 |
Michael Pavone |
Properly clear trace mode on interrupt or other exception. Fix NBCD with memory destination
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| Fri, 11 Aug 2017 18:43:48 -0700 |
Michael Pavone |
Avoid generating an instruction that would require a REX prefix when a7 is used as a byte-wide source operand in 32-bit builds. Fixes a fatal error in Dragon's Fury when entering the option menu in a 32-bit build
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| Fri, 26 May 2017 19:18:19 -0700 |
Michael Pavone |
Avoid splitting m68k_check_cycles_int_latch code across memory chunks since it expects a byte-sized jump offset. Avoid an unnecessary m68k_check_cycles_int_latch for register to register moves
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| Tue, 23 May 2017 21:07:56 -0700 |
Michael Pavone |
Fix interrupt latency for move.l with memory destination
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| Fri, 19 May 2017 20:27:35 -0700 |
Michael Pavone |
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
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| Wed, 26 Apr 2017 21:55:12 -0700 |
Michael Pavone |
Fix timing for branch not taken case in the M68K BCC intruction
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| Mon, 24 Apr 2017 20:49:31 -0700 |
Michael Pavone |
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
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| Tue, 28 Mar 2017 09:39:54 -0700 |
Michael Pavone |
Fix exit trace mode edge case. Call do_sync if trace mode bit is changed in eori sr
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| Tue, 28 Mar 2017 00:13:35 -0700 |
Michael Pavone |
Implemented M68K trace mode. Some edge cases/SR update paths still need work
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| Wed, 22 Mar 2017 22:16:39 -0700 |
Michael Pavone |
Fix SBCD edge cases to pass Flamewing's test ROM. Could use some cleanup to produce better code for the SBCD case, but produces correct results now
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| Fri, 17 Mar 2017 08:05:55 -0700 |
Michael Pavone |
Minor fix to timing of "early" overflow case in divs when the dividend is negative
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| Wed, 15 Mar 2017 19:05:27 -0700 |
Michael Pavone |
Cycle accurate implementation of divs
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| Thu, 09 Mar 2017 23:50:46 -0800 |
Michael Pavone |
Fix undefined flags on overflow and divide by zero for divu based on hardware test. Fix saving result of divu when destination is not stored in a host register
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