| Tue, 30 Aug 2022 18:42:45 -0700 |
Michael Pavone |
Add disassemble command to debugger
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| Tue, 18 Jan 2022 00:03:50 -0800 |
Michael Pavone |
Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
segacd
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| Thu, 17 May 2018 00:43:16 -0700 |
Michael Pavone |
Fix instruction timing for a number of instructions with only a single operand
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| Fri, 19 May 2017 20:27:35 -0700 |
Michael Pavone |
Fix to M68K interrupt latency for most instructions. Still needs some work for RAW_IMPL instructions besides move
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| Mon, 24 Apr 2017 20:49:31 -0700 |
Michael Pavone |
Fix interaction between 68K debugger and instruction retranslation due to self modifying code or bank switching
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| Wed, 15 Mar 2017 19:05:27 -0700 |
Michael Pavone |
Cycle accurate implementation of divs
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| Fri, 03 Mar 2017 23:51:29 -0800 |
Michael Pavone |
Cycle accurate divu and undefined flags for overflow case
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| Mon, 28 Nov 2016 22:45:46 -0800 |
Michael Pavone |
Clean up symbol visiblity and delete a ltitle bit of dead code
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| Thu, 06 Oct 2016 09:34:31 -0700 |
Michael Pavone |
Add support for specifying a reset handler in the M68K core. Adjust memory map initialization to handle extra field. Improved handling of out of bounds execution.
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| Wed, 27 Apr 2016 23:11:24 -0700 |
Michael Pavone |
Implement privelege violation exceptions
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| Tue, 26 Apr 2016 23:13:37 -0700 |
Michael Pavone |
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
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| Tue, 26 Apr 2016 00:07:15 -0700 |
Michael Pavone |
Implement illegal instruction trap
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| Sun, 24 Apr 2016 02:19:48 -0700 |
Michael Pavone |
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
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| Sun, 24 Apr 2016 00:22:38 -0700 |
Michael Pavone |
Fix order of writes for move.l with a predec destination
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| Thu, 29 Oct 2015 19:06:06 -0700 |
Michael Pavone |
Implement TRAPV
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