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changeset 1942:35722beaf895

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Fix instruction timing for addq.w #i, (ay) in dynarec
author Michael Pavone <pavone@retrodev.com>
date Sat, 25 Apr 2020 18:10:40 -0700
parents 9eec86183aae
children 794a5c9a2c73
files m68k_core_x86.c
diffstat 1 files changed, 0 insertions(+), 2 deletions(-) [+]
line wrap: on
line diff
--- a/m68k_core_x86.c	Fri Apr 24 09:23:43 2020 -0700
+++ b/m68k_core_x86.c	Sat Apr 25 18:10:40 2020 -0700
@@ -1315,8 +1315,6 @@
 			numcycles = 6;
 		} else if (inst->op == M68K_AND && inst->variant == VAR_IMMEDIATE) {
 			numcycles = 6;
-		} else if (inst->op == M68K_ADD && inst->dst.addr_mode == MODE_AREG && inst->extra.size == OPSIZE_WORD && inst->variant == VAR_QUICK) {
-			numcycles = 4;
 		} else if (inst->dst.addr_mode <= MODE_AREG) {
 			numcycles = inst->src.addr_mode <= MODE_AREG || inst->src.addr_mode == MODE_IMMEDIATE ? 8 : 6;
 		} else {