changeset 2584:5851240f71c9

Implement scc in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sat, 08 Feb 2025 14:27:04 -0800
parents 0f7609fe03f2
children c730067d5f77
files m68k.cpu
diffstat 1 files changed, 21 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/m68k.cpu	Sat Feb 08 13:34:46 2025 -0800
+++ b/m68k.cpu	Sat Feb 08 14:27:04 2025 -0800
@@ -2550,6 +2550,27 @@
 		invert |= zflag
 	end
 
+0101CCCC11MMMDDD scc
+	invalid M 1
+	invalid M 7 D 2
+	invalid M 7 D 3
+	invalid M 7 D 4
+	invalid M 7 D 5
+	invalid M 7 D 6
+	invalid M 7 D 7
+	m68k_fetch_dst_ea M D 0
+	m68k_check_cond C
+	if istrue
+		if M = 0
+			cycles 2
+		end
+		dst:0 = 0xFF
+	else
+		dst:0 = 0
+	end
+	m68k_save_dst 0
+	m68k_prefetch
+
 0110CCCC00000000 bcc_w
 	#mid-instruction timing isn't quite right
 	#becuase I'm only emulating a 1-word prefetch buffer instead of 2