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changeset 247:682e505f5757

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Implement rotation and bit set/reset instructions (untested).
author Mike Pavone <pavone@retrodev.com>
date Sun, 28 Apr 2013 22:41:30 -0700
parents ed548c77b598
children 9c7a3db7bcd0
files z80_to_x86.c z80inst.c
diffstat 2 files changed, 126 insertions(+), 12 deletions(-) [+]
line wrap: on
line diff
--- a/z80_to_x86.c	Sun Apr 28 21:00:27 2013 -0700
+++ b/z80_to_x86.c	Sun Apr 28 22:41:30 2013 -0700
@@ -659,11 +659,101 @@
 		dst = zcycles(dst, 4);
 		dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B);
 		break;
-	/*case Z80_RLC:
+	case Z80_RLC:
+		cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
+		dst = zcycles(dst, cycles);
+		if (inst->reg == Z80_UNUSED) {
+			dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
+			dst = zcycles(dst, 1);
+		} else {
+			dst = translate_z80_reg(inst, &dst_op, dst, opts);
+		}
+		dst = rol_ir(dst, 1, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
+		dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
+		//TODO: Implement half-carry flag
+		dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
+		dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
+		dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
+		if (inst->reg == Z80_UNUSED) {
+			dst = z80_save_result(dst, inst);
+		} else {
+			dst = z80_save_reg(dst, inst, opts);
+		}
+		break;
 	case Z80_RL:
+		cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
+		dst = zcycles(dst, cycles);
+		if (inst->reg == Z80_UNUSED) {
+			dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
+			dst = zcycles(dst, 1);
+		} else {
+			dst = translate_z80_reg(inst, &dst_op, dst, opts);
+		}
+		dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
+		dst = rcl_ir(dst, 1, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
+		dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
+		//TODO: Implement half-carry flag
+		dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
+		dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
+		dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
+		if (inst->reg == Z80_UNUSED) {
+			dst = z80_save_result(dst, inst);
+		} else {
+			dst = z80_save_reg(dst, inst, opts);
+		}
+		break;
 	case Z80_RRC:
+		cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
+		dst = zcycles(dst, cycles);
+		if (inst->reg == Z80_UNUSED) {
+			dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
+			dst = zcycles(dst, 1);
+		} else {
+			dst = translate_z80_reg(inst, &dst_op, dst, opts);
+		}
+		dst = ror_ir(dst, 1, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
+		dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
+		//TODO: Implement half-carry flag
+		dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
+		dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
+		dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
+		if (inst->reg == Z80_UNUSED) {
+			dst = z80_save_result(dst, inst);
+		} else {
+			dst = z80_save_reg(dst, inst, opts);
+		}
+		break;
 	case Z80_RR:
-	case Z80_SLA:
+		cycles = inst->immed == 1 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
+		dst = zcycles(dst, cycles);
+		if (inst->reg == Z80_UNUSED) {
+			dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
+			dst = zcycles(dst, 1);
+		} else {
+			dst = translate_z80_reg(inst, &dst_op, dst, opts);
+		}
+		dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
+		dst = rcr_ir(dst, 1, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
+		dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
+		//TODO: Implement half-carry flag
+		dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
+		dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
+		dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
+		dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
+		if (inst->reg == Z80_UNUSED) {
+			dst = z80_save_result(dst, inst);
+		} else {
+			dst = z80_save_reg(dst, inst, opts);
+		}
+		break;
+	/*case Z80_SLA:
 	case Z80_SRA:
 	case Z80_SLL:
 	case Z80_SRL:
@@ -680,8 +770,32 @@
 		dst = bt_ir(dst, inst->immed, src_op.base, SZ_B);
 		dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z));
 		break;
-	//case Z80_SET:
-	//case Z80_RES:
+	case Z80_SET:
+		cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
+		dst = zcycles(dst, cycles);
+		dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
+		if (inst->addr_mode != Z80_REG) {
+			//Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
+			dst = zcycles(dst, 1);
+		}
+		dst = bts_ir(dst, inst->immed, src_op.base, SZ_B);
+		if (inst->addr_mode != Z80_REG) {
+			dst = z80_save_result(dst, inst);
+		}
+		break;
+	case Z80_RES:
+		cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
+		dst = zcycles(dst, cycles);
+		dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
+		if (inst->addr_mode != Z80_REG) {
+			//Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
+			dst = zcycles(dst, 1);
+		}
+		dst = btr_ir(dst, inst->immed, src_op.base, SZ_B);
+		if (inst->addr_mode != Z80_REG) {
+			dst = z80_save_result(dst, inst);
+		}
+		break;
 	case Z80_JP: {
 		cycles = 4;
 		if (inst->addr_mode != Z80_REG) {
--- a/z80inst.c	Sun Apr 28 21:00:27 2013 -0700
+++ b/z80inst.c	Sun Apr 28 22:41:30 2013 -0700
@@ -420,14 +420,14 @@
 };
 
 #define SHIFT_BLOCK(op) \
-	{op, Z80_B, Z80_UNUSED, Z80_UNUSED, 0},\
-	{op, Z80_C, Z80_UNUSED, Z80_UNUSED, 0},\
-	{op, Z80_D, Z80_UNUSED, Z80_UNUSED, 0},\
-	{op, Z80_E, Z80_UNUSED, Z80_UNUSED, 0},\
-	{op, Z80_H, Z80_UNUSED, Z80_UNUSED, 0},\
-	{op, Z80_L, Z80_UNUSED, Z80_UNUSED, 0},\
-	{op, Z80_UNUSED, Z80_REG_INDIRECT, Z80_HL, 0},\
-	{op, Z80_A, Z80_UNUSED, Z80_UNUSED, 0}
+	{op, Z80_B, Z80_UNUSED, Z80_UNUSED, 1},\
+	{op, Z80_C, Z80_UNUSED, Z80_UNUSED, 1},\
+	{op, Z80_D, Z80_UNUSED, Z80_UNUSED, 1},\
+	{op, Z80_E, Z80_UNUSED, Z80_UNUSED, 1},\
+	{op, Z80_H, Z80_UNUSED, Z80_UNUSED, 1},\
+	{op, Z80_L, Z80_UNUSED, Z80_UNUSED, 1},\
+	{op, Z80_UNUSED, Z80_REG_INDIRECT, Z80_HL, 1},\
+	{op, Z80_A, Z80_UNUSED, Z80_UNUSED, 1}
 	
 #define BIT_BLOCK(op, bit) \
 	{op, Z80_USE_IMMED, Z80_REG, Z80_B, bit},\