--- a/gen_arm.c	Tue Jan 06 19:09:00 2015 -0800
+++ b/gen_arm.c	Thu Jan 08 07:49:16 2015 +0100
@@ -548,3 +548,39 @@
 	*(code->cur++) = cc | POPM | reglist;
 	return CODE_OK;
 }
+
+uint32_t load_store_immoff(code_info *code, uint32_t op, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc)
+{
+	if (offset >= 0x1000 || offset <= -0x1000) {
+		return INVALID_IMMED;
+	}
+	check_alloc_code(code);
+	uint32_t instruction = cc | op | POST_IND | OFF_IMM | SZ_W | base << 16 | dst << 12;
+	if (offset >= 0) {
+		instruction |= offset | DIR_UP;
+	} else {
+		instruction |= (-offset) | DIR_DOWN;
+	}
+	*(code->cur++) = instruction;
+	return CODE_OK;
+}
+
+uint32_t ldr_cc(code_info *code, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc)
+{
+	return load_store_immoff(code, OP_LDR, dst, base, offset, cc);
+}
+
+uint32_t ldr(code_info *code, uint32_t dst, uint32_t base, int32_t offset)
+{
+	return ldr_cc(code, dst, base, offset, CC_AL);
+}
+
+uint32_t str_cc(code_info *code, uint32_t src, uint32_t base, int32_t offset, uint32_t cc)
+{
+	return load_store_immoff(code, OP_STR, src, base, offset, cc);
+}
+
+uint32_t str(code_info *code, uint32_t src, uint32_t base, int32_t offset)
+{
+	return str_cc(code, src, base, offset, CC_AL);
+}

--- a/gen_arm.h	Tue Jan 06 19:09:00 2015 -0800
+++ b/gen_arm.h	Thu Jan 08 07:49:16 2015 +0100
@@ -149,5 +149,9 @@
 uint32_t pop_cc(code_info *code, uint32_t reg, uint32_t cc);
 uint32_t popm(code_info *code, uint32_t reglist);
 uint32_t popm_cc(code_info *code, uint32_t reglist, uint32_t cc);
+uint32_t ldr_cc(code_info *code, uint32_t dst, uint32_t base, int32_t offset, uint32_t cc);
+uint32_t ldr(code_info *code, uint32_t rst, uint32_t base, int32_t offset);
+uint32_t str_cc(code_info *code, uint32_t src, uint32_t base, int32_t offset, uint32_t cc);
+uint32_t str(code_info *code, uint32_t src, uint32_t base, int32_t offset);
 
 #endif //GEN_ARM_H_