Mercurial > repos > blastem

changeset 2578:9b01541cbd60

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix rol and ror in new CPU core
author Michael Pavone <pavone@retrodev.com>
date Fri, 07 Feb 2025 19:58:20 -0800
parents 5f725429d08f
children bd8d1babbfb5
files cpu_dsl.py m68k.cpu
diffstat 2 files changed, 49 insertions(+), 62 deletions(-) [+]
line wrap: on
line diff
--- a/cpu_dsl.py	Fri Feb 07 08:57:24 2025 -0800
+++ b/cpu_dsl.py	Fri Feb 07 19:58:20 2025 -0800
@@ -546,23 +546,23 @@
 						resultBit = f'({prog.getLastSize()} - {prog.lastB})'
 					myRes = prog.lastA
 				elif prog.lastOp.op == 'rol':
-					if type(prog.lastB) is int:
-						if prog.lastB == 0:
+					if type(prog.lastBUnmasked) is int:
+						if prog.lastBUnmasked == 0:
 							explicit[flag] = 0
 							continue
 					else:
-						output.append(f'\n\tif (!{prog.lastB}) {{')
+						output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
 						_addExplicitFlagSet(prog, output, flag, 0)
 						output.append('\n\t} else {')
 						after = '\n\t}'
 					resultBit = 0
 				elif prog.lastOp.op == 'ror':
-					if type(prog.lastB) is int:
-						if prog.lastB == 0:
+					if type(prog.lastBUnmasked) is int:
+						if prog.lastBUnmasked == 0:
 							explicit[flag] = 0
 							continue
 					else:
-						output.append(f'\n\tif (!{prog.lastB}) {{')
+						output.append(f'\n\tif (!{prog.lastBUnmasked}) {{')
 						_addExplicitFlagSet(prog, output, flag, 0)
 						output.append('\n\t} else {')
 						after = '\n\t}'
@@ -976,7 +976,6 @@
 			calc = prog.flags.flagCalc[flag]
 			if calc == 'carry':
 				needsCarry = True
-	decl = ''
 	destSize = prog.paramSize(rawParams[2])
 	needsSizeAdjust = False
 	if len(params) > 3:
@@ -994,20 +993,29 @@
 				prog.sizeAdjust = size
 	else:
 		size = destSize
-	
-	prog.lastB = params[1]
+	rotMask = size - 1
+	if type(params[1]) is int:
+		b = params[1] & rotMask
+		mdecl = ''
+		ret = ''
+	else:
+		mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
+		ret = f'\n\t{b} = {params[1]} & {rotMask};'
+	prog.lastB = b
+	prog.lastBUnmasked = params[1]
 	if needsSizeAdjust:
 		decl,name = prog.getTemp(size)
+		mdecl += decl
 		dst = prog.carryFlowDst = name
 	else:
 		dst = params[2]
-	ret = decl + '\n\t{dst} = {a} << {b} | {a} >> ({size} - {b});'.format(dst = dst,
-		a = params[0], b = params[1], size=size
+	ret += '\n\t{dst} = {a} << {b} | {a} >> ({size} - {b});'.format(dst = dst,
+		a = params[0], b = b, size=size
 	)
 	if needsSizeAdjust and not needsCarry:
 		mask = (1 << size) - 1
 		ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) | ({dst} & {mask});'
-	return ret
+	return mdecl + ret
 	
 def _rlcCImpl(prog, params, rawParams, flagUpdates):
 	needsCarry = False
@@ -1063,7 +1071,6 @@
 			calc = prog.flags.flagCalc[flag]
 			if calc == 'carry':
 				needsCarry = True
-	decl = ''
 	destSize = prog.paramSize(rawParams[2])
 	needsSizeAdjust = False
 	if len(params) > 3:
@@ -1081,19 +1088,29 @@
 				prog.sizeAdjust = size
 	else:
 		size = destSize
-	prog.lastB = params[1]
+	rotMask = size - 1
+	if type(params[1]) is int:
+		b = params[1] & rotMask
+		mdecl = ''
+		ret = ''
+	else:
+		mdecl,b = prog.getTemp(prog.paramSize(rawParams[1]))
+		ret = f'\n\t{b} = {params[1]} & {rotMask};'
+	prog.lastB = b
+	prog.lastBUnmasked = params[1]
 	if needsSizeAdjust:
 		decl,name = prog.getTemp(size)
 		dst = prog.carryFlowDst = name
+		mdecl += decl
 	else:
 		dst = params[2]
-	ret = decl + '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = dst,
-		a = params[0], b = params[1], size=size
+	ret += '\n\t{dst} = {a} >> {b} | {a} << ({size} - {b});'.format(dst = dst,
+		a = params[0], b = b, size=size
 	)
 	if needsSizeAdjust and not needsCarry:
 		mask = (1 << size) - 1
 		ret += f'\n\t{params[2]} = ({params[2]} & ~{mask}) | ({dst} & {mask});'
-	return ret
+	return mdecl + ret
 
 def _rrcCImpl(prog, params, rawParams, flagUpdates):
 	needsCarry = False
--- a/m68k.cpu	Fri Feb 07 08:57:24 2025 -0800
+++ b/m68k.cpu	Fri Feb 07 19:58:20 2025 -0800
@@ -2587,32 +2587,17 @@
 1110CCC0ZZ111RRR ror_dn
 	invalid Z 3
 	local shift 8
-	local cycle_shift 8
-	cycle_shift = dregs.C & 63
+	shift = dregs.C & 63
+	ror dregs.R shift dregs.R Z
+	update_flags NZV0C
+	shift += shift
 	switch Z
 	case 2
-		if cycle_shift = 32
-			ror dregs.R 31 dregs.R Z
-			ror dregs.R 1 dregs.R Z
-			update_flags NZV0C
-		else
-			shift = dregs.C & 31
-			ror dregs.R shift dregs.R Z
-			update_flags NZV0C
-		end
+		shift += 4
 	default
-		shift = dregs.C & 31
-		ror dregs.R shift dregs.R Z
-		update_flags NZV0C
+		shift += 2
 	end
-	cycle_shift += cycle_shift
-	switch Z
-	case 2
-		cycle_shift += 4
-	default
-		cycle_shift += 2
-	end
-	cycles cycle_shift
+	cycles shift
 	#TODO: should this happen before or after the majority of the rotate?
 	m68k_prefetch
 
@@ -2628,7 +2613,7 @@
 	
 	m68k_fetch_dst_ea M R 1
 	ror dst 1 dst 1
-	update_flags XNZV0C
+	update_flags NZV0C
 	m68k_save_dst 1
 	m68k_prefetch
 
@@ -2657,32 +2642,17 @@
 1110CCC1ZZ111RRR rol_dn
 	invalid Z 3
 	local shift 8
-	local cycle_shift 8
-	cycle_shift = dregs.C & 63
+	shift = dregs.C & 63
+	rol dregs.R shift dregs.R Z
+	update_flags NZV0C
+	shift += shift
 	switch Z
 	case 2
-		if cycle_shift = 32
-			rol dregs.R 31 dregs.R Z
-			rol dregs.R 1 dregs.R Z
-			update_flags NZV0C
-		else
-			shift = dregs.C & 31
-			rol dregs.R shift dregs.R Z
-			update_flags NZV0C
-		end
+		shift += 4
 	default
-		shift = dregs.C & 31
-		rol dregs.R shift dregs.R Z
-		update_flags NZV0C
+		shift += 2
 	end
-	cycle_shift += cycle_shift
-	switch Z
-	case 2
-		cycle_shift += 4
-	default
-		cycle_shift += 2
-	end
-	cycles cycle_shift
+	cycles shift
 	#TODO: should this happen before or after the majority of the rotate?
 	m68k_prefetch