Mercurial > repos > blastem
changeset 331:de17e0352f27
Fixup VINT cycle and HBLANK flag for the previous timing fixes
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Tue, 14 May 2013 00:03:26 -0700 |
| parents | 57453d3d8be4 |
| children | 671a5be51522 |
| files | vdp.c |
| diffstat | 1 files changed, 9 insertions(+), 7 deletions(-) [+] |
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--- a/vdp.c Mon May 13 23:42:52 2013 -0700 +++ b/vdp.c Tue May 14 00:03:26 2013 -0700 @@ -36,13 +36,16 @@ #define FIFO_SIZE 4 -#define VINT_SLOTS_H40 (21+16+10) //21 slots before HSYNC, 16 during, 10 after TODO: deal with clock switching during HSYNC -#define VINT_SLOTS_H32 (33+20+7) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number #define MCLKS_SLOT_H40 16 #define MCLKS_SLOT_H32 20 +#define VINT_CYCLE_H40 (21*MCLKS_SLOT_H40+332+9*MCLKS_SLOT_H40) //21 slots before HSYNC, 16 during, 10 after +#define VINT_CYCLE_H32 ((33+20+7)*MCLKS_SLOT_H32) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number #define HSYNC_SLOT_H40 21 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) +#define HSYNC_END_H32 (33 * MCLKS_SLOT_H32) +#define HBLANK_CLEAR_H40 (MCLK_WEIRD_END+61*4) +#define HBLANK_CLEAR_H32 (HSYNC_END_H32 + 46*5) void init_vdp_context(vdp_context * context) { @@ -1122,7 +1125,7 @@ context->hint_counter = context->regs[REG_HINT]; } } else if(line == active_lines) { - uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_SLOTS_H40 * MCLKS_SLOT_H40 : VINT_SLOTS_H32 * MCLKS_SLOT_H32; + uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_CYCLE_H40 : VINT_CYCLE_H32; if (linecyc == intcyc) { context->flags2 |= FLAG2_VINT_PENDING; } @@ -1364,7 +1367,7 @@ if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { value |= 0x8; } - if (linecyc < (context->latched_mode & BIT_H40 ? (148 + 61) * 4 : ( + 46) * 5)) { + if (linecyc < (context->latched_mode & BIT_H40 ? HBLANK_CLEAR_H40 : HBLANK_CLEAR_H32)) { value |= 0x4; } if (context->flags & FLAG_DMA_RUN) { @@ -1485,7 +1488,6 @@ uint32_t vdp_next_vint(vdp_context * context) { - //TODO: deal with clock adjustemnts handled in vdp_run_context if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { return 0xFFFFFFFF; } @@ -1495,9 +1497,9 @@ uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; uint32_t vcycle = MCLKS_LINE * active_lines; if (context->latched_mode & BIT_H40) { - vcycle += VINT_SLOTS_H40 * MCLKS_SLOT_H40; + vcycle += VINT_CYCLE_H40; } else { - vcycle += VINT_SLOTS_H32 * MCLKS_SLOT_H32; + vcycle += VINT_CYCLE_H32; } if (vcycle < context->cycles) { return 0xFFFFFFFF;