| Tue, 27 Dec 2016 13:38:58 -0800 |
Michael Pavone |
The function of the HVC Latch enable bit in mode register 1 is different when not in mode 5
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| Tue, 27 Dec 2016 13:26:14 -0800 |
Michael Pavone |
Fix inactive start line for Mode 4 in vdp_next_hint. Fix an off by one error in the range of registers allowed to be written in Mode 4
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| Tue, 27 Dec 2016 13:11:07 -0800 |
Michael Pavone |
Implemented Mode 4 sprite list termination
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| Tue, 27 Dec 2016 12:43:37 -0800 |
Michael Pavone |
Less broken Mode 4 implementation
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| Tue, 27 Dec 2016 11:31:17 -0800 |
Michael Pavone |
Somewhat broken implementation of Mode 4
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| Thu, 22 Dec 2016 20:39:35 -0800 |
Michael Pavone |
Fix clearing of interrupt pending flags on control port read in PBC mode
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| Thu, 22 Dec 2016 19:54:11 -0800 |
Michael Pavone |
Added Jaguar header missed in earlier commits
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| Thu, 22 Dec 2016 19:51:25 -0800 |
Michael Pavone |
Initial support for Genesis/Megadrive PBC mode. VDP still needs Mode 4 to be useful.
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| Thu, 22 Dec 2016 10:51:33 -0800 |
Michael Pavone |
More cleanup in preparation for SMS/Mark III support
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| Mon, 19 Dec 2016 14:16:59 -0800 |
Michael Pavone |
WIP Jaguar GPU/DSP emulation
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| Mon, 19 Dec 2016 14:16:43 -0800 |
Michael Pavone |
Fix blastjag target
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| Mon, 19 Dec 2016 13:58:51 -0800 |
Michael Pavone |
Restore 68K address logging functionality
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| Mon, 19 Dec 2016 13:46:58 -0800 |
Michael Pavone |
Fix intermittent crash in GST savestate loading
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| Mon, 19 Dec 2016 13:28:18 -0800 |
Michael Pavone |
Mostly working changes to allow support for multiple emulated system types in main blastem program
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| Wed, 14 Dec 2016 23:27:42 -0800 |
Michael Pavone |
Fix a couple of timing regressions in Z80 core
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