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Apply register assignments in il module
author Mike Pavone <pavone@retrodev.com>
date Mon, 26 Aug 2013 20:42:20 -0700
parents 4293c725394c
children 7856f0916549
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1 {
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2 //commutative ops
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3 _add <- 0
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4 _and <- 1
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5 _or <- 2
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6 _xor <- 3
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7 //non-commutative ops
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8 _sub <- 4
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9 _cmp <- 5
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10 _not <- 6
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11 _sl <- 7
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12 _asr <- 8
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13 _lsr <- 9
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14 _rol <- 10
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15 _ror <- 11
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16 _mov <- 12
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17 _call <- 13
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18 _ret <- 14
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19 _skipif <- 15
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20
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21 _names <- #[
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22 "add"
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23 "and"
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24 "or"
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25 "xor"
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26 "sub"
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27 "cmp"
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28 "not"
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29 "sl"
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30 "asr"
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31 "lsr"
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32 "rol"
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33 "ror"
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34 "mov"
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35 "call"
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36 "ret"
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37 "skipIf"
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38 ]
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39
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40 op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
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41 #{
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42 opcode <- { _opcode }
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43 ina <- { _ina }
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44 inb <- { _inb }
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45 commutative? <- { _opcode < _sub }
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46 out <- { _out }
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47 size <- { _size }
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48 numops <- { 3 }
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49 name <- { _names get: _opcode }
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50 string <- { name . " " . (string: _ina) . " " . (string: _inb) . " " . (string: _out) . " " . (string: _size) }
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51 recordUsage:at <- :tracker :address {
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52 if: (not: (_ina isInteger?)) {
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53 _ina recordUsage: tracker at: 0 | address withSize: _size
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54 }
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55 _inb recordUsage: tracker at: 0 | address withSize: _size
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56 _out recordUsage: tracker at: 1 | address withSize: _size
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57 }
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58 assignRegs:withSource <- :assignments :regSrc {
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59 newa <- if: (not: (_ina isInteger?)) {
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60 _ina assign: assignments withSource: regSrc
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61 } else: { _ina }
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62 newb <- _inb assign: assignments withSource: regSrc
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63 newout <- _out assign: assignments withSource: regSrc
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64 op3: _opcode a: newa b: newb out: newout size: _size
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65 }
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66 }
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67 }
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68 op2:in:out:size <- :_opcode :_in :_out :_size {
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69 #{
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70 opcode <- { _opcode }
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71 in <- { _in }
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72 out <- { _out }
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73 size <- { _size }
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74 numops <- { 2 }
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75 name <- { _names get: _opcode }
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76 string <- { name . " " . (string: _in) . " " . (string: _out) . " " . (string: _size) }
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77 recordUsage:at <- :tracker :address {
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78 if: (not: (_in isInteger?)) {
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79 _in recordUsage: tracker at: 0 | address withSize: _size
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80 }
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81 _out recordUsage: tracker at: 1 | address withSize: _size
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82 }
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83 assignRegs:withSource <- :assignments :regSrc {
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84 newin <- if: (not: (_in isInteger?)) {
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85 _in assign: assignments withSource: regSrc
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86 } else: { _in }
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87 newout <- _out assign: assignments withSource: regSrc
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88 op2: _opcode in: newin out: newout size: _size
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89 }
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90 }
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91 }
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92 op1:arg:size <- :_opcode :_arg :_size {
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93 #{
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94 opcode <- { _opcode }
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95 arg <- { _arg }
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96 size <- { _size }
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97 numops <- { 1 }
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98 name <- { _names get: _opcode }
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99 string <- { name . " " . (string: _arg) . " " . (string: _size) }
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100 recordUsage:at <- :tracker :address {
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101 if: (not: (_arg isInteger?)) {
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102 _arg recordUsage: tracker at: address withSize: _size
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103 }
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104 }
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105 assignRegs:withSource <- :assignments :regSrc {
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106 newarg <- if: (not: (_arg isInteger?)) {
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107 _arg assign: assignments withSource: regSrc
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108 } else: { _arg }
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109 op1: _opcode arg: newarg size: _size
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110 }
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111 }
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112 }
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113
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114 _sizenames <- #["b" "w" "l" "q"]
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115 _size <- :_bytes {
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116 #{
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117 bytes <- { _bytes }
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118 string <- {
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119 idx <- if: _bytes = 8 { 3 } else: { _bytes / 2}
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120 _sizenames get: idx
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121 }
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122 = <- :other {
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123 _bytes = (other bytes)
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124 }
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125 <= <- :other {
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126 _bytes <= (other bytes)
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127 }
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128 >= <- :other {
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129 _bytes >= (other bytes)
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130 }
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131 > <- :other {
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132 _bytes > (other bytes)
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133 }
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134 < <- :other {
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135 _bytes < (other bytes)
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136 }
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137 }
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138 }
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139 byte <- _size: 1
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140 word <- _size: 2
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141 long <- _size: 4
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142 quad <- _size: 8
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143
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144 _retr <- #{
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145 isInteger? <- { false }
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146 register? <- { true }
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147 argument? <- { false }
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148 return? <- { true }
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149 string <- { "retr" }
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150 = <- :other {
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151 (not: (other isInteger?)) && (other register?) && (other return?)
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152 }
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153 != <- :other {
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154 not: self = other
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155 }
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156 recordUsage:at:withSize <- :tracker :address :size {
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157 //TODO: Figure out what tracking is necessary here
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158 }
194
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159 assign:withSource <- :assignments :regSrc {
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160 regSrc allocRet
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161 }
185
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162 }
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163
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164 _condnames <- #[
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165 "eq"
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166 "neq"
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167 "ge"
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168 "le"
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169 "gr"
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170 "ls"
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171 "uge"
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172 "ule"
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173 "ugr"
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174 "uls"
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175 ]
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176 condition <- :num {
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177 #{
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178 cc <- { num }
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179 string <- { _condnames get: num }
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180 = <- :other { num = (other cc) }
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181 }
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182 }
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183 _eq <- condition: 0
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184 _neq <- condition: 1
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185 _ge <- condition: 2
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186 _le <- condition: 3
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187 _gr <- condition: 4
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188 _ls <- condition: 5
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189 _uge <- condition: 6
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190 _ule <- condition: 7
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191 _ugr <- condition: 8
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192 _uls <- condition: 9
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193
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194 #{
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195 b <- { byte }
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196 w <- { word }
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197 l <- { long }
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198 q <- { quad }
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199
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200 eq <- { _eq }
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201 neq <- { _neq }
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202
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203 //signed conditions
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204 ge <- { _ge }
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205 le <- { _le }
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206 gr <- { _gr }
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207 ls <- { _ls }
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208
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209 //unsigned conditions
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210 uge <- { _uge }
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211 ule <- { _ule }
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212 ugr <- { _ugr }
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213 uls <- { _uls }
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214
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215
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216 reg <- :num {
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217 #{
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218 isInteger? <- { false }
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219 register? <- { true }
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220 argument? <- { false }
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221 return? <- { false }
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222 regnum <- { num }
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223 string <- { "r" . (string: num) }
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224 = <- :other {
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225 (not: (other isInteger?)) && (other register?) && (not: (other argument?)) && (not: (other return?)) && num = (other regnum)
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226 }
189
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227 != <- :other {
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228 not: self = other
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229 }
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230 recordUsage:at:withSize <- :tracker :address :size {
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231 tracker reg: self usedAt: address withSize: size
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232 }
194
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233 assign:withSource <- :assignments :regSrc {
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234 assignments get: self
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235 }
185
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236 }
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237 }
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238 arg <- :num {
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239 #{
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240 isInteger? <- { false }
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241 register? <- { true }
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242 argument? <- { true }
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243 return? <- { false }
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244 argnum <- { num }
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245 string <- { "a" . (string: num) }
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246 = <- :other {
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247 (not: (other isInteger?)) && (other register?) && (other argument?) && num = (other regnum)
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248 }
189
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249 != <- :other {
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250 not: self = other
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251 }
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252 recordUsage:at:withSize <- :tracker :address :size {
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253 tracker arg: self usedAt: address withSize: size
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254 }
194
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255 assign:withSource <- :assignments :regSrc {
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256 regSrc allocArg: num
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257 }
185
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258 }
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259 }
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260 retr <- { _retr }
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261
189
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262 base:offset <- :_base :_offset {
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263 #{
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264 base <- { _base }
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265 offset <- { _offset }
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266 string <- {
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267 start <- if: _offset = 0 { "" } else: { (string: _offset) }
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268 start . "[" . (string: _base) . "]"
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269 }
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270 recordUsage:at:withSize <- :tracker :address :size {
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271 _base recordUsage: tracker at: address withSize: size
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272 }
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273 }
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274 }
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275
185
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276 add <- :ina inb out size {
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277 op3: _add a: ina b: inb out: out size: size
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278 }
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279
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280 sub <- :ina inb out size {
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281 op3: _sub a: ina b: inb out: out size: size
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282 }
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283
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284 cmp <- :ina inb out size {
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285 op3: _cmp a: ina b: inb out: out size: size
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286 }
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287
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288 and <- :ina inb out size {
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289 op3: _and a: ina b: inb out: out size: size
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290 }
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291
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292 or <- :ina inb out size {
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293 op3: _or a: ina b: inb out: out size: size
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294 }
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295
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296 xor <- :ina inb out size {
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297 op3: _xor a: ina b: inb out: out size: size
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298 }
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299
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300 bnot <- :in out size {
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301 op2: _not in: in out: out size: size
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302 }
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303
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304 sl <- :shift in out size {
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305 op3: _sl a: shift b: in out: out size: size
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306 }
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307
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308 asr <- :shift in out size {
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309 op3: _asr a: shift b: in out: out size: size
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310 }
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311
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312 lsr <- :shift in out size {
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313 op3: _lsr a: shift b: in out: out size: size
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314 }
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315
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316 rol <- :rot in out size {
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317 op3: _rol a: rot b: in out: out size: size
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318 }
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319
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320 ror <- :rot in out size {
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321 op3: _ror a: rot b: in out: out size: size
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322 }
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323
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324 mov <- :in out size {
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325 op2: _mov in: in out: out size: size
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326 }
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327
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328 call:withArgs <- :_target :_args {
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329 #{
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330 opcode <- { _call }
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331 target <- { _target }
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332 args <- { _args }
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333 numops <- { 0 }
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334 name <- { _names get: _call }
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335 string <- {
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336 argstr <- _args map: :el {
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337 string: el
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338 }
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339 name . " " . (string: _target) . " " . (argstr join: " ")
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340 }
189
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341 recordUsage:at <- :tracker :address {
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342 if: (not: (_target isString?)) {
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343 //TODO: use size l for 32-bit targets or an abstract pointer size
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344 _target recordUsage: tracker at: address withSize: q
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345 }
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346 foreach: _args :_ arg {
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347 //TODO: have some mechanism for properly expressing sizes of arguments
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348 arg recordUsage: tracker at: address withSize: q
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349 }
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350 }
194
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351 assignRegs:withSource <- :assignments :regSrc {
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352 newtarget <- if: (_target isString?) { _target } else: {
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353 _target assign: assignments withSource: regSrc
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354 }
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355 newargs <- _args map: :arg {
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356 if: (arg isInteger?) { arg } else: {
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357 arg assign: assignments withSource: regSrc
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358 }
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359 }
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360 //TODO: Save caller-save regs if necessary
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361 //TODO: Add instructions for moving arguments to proper regs/stack locations
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362 call: newtarget withArgs: newargs
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363 }
185
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364 }
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365 }
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366
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367 return <- :val size {
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368 op1: _ret arg: val size: size
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369 }
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370 skipIf <- :_cond _toskip {
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371 #{
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372 opcode <- { _skipif }
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373 toskip <- { _toskip }
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374 cond <- { _cond }
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375 numops <- { 0 }
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376 name <- { _names get: _skipif }
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377 string <- {
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378 block <- (_toskip map: :el { string: el }) join: "\n\t"
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379 if: (_toskip length) > 0 {
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380 block <- "\n\t" . block . "\n"
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381 }
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382 name . " " . (string: _cond) . " {" . block . "}"
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383 }
189
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384 recordUsage:at <- :tracker :address {
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385 foreach: _toskip :idx inst {
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386 inst recordUsage: tracker at: idx | address
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387 }
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388 }
194
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389 assignRegs:withSource <- :assignments :regSrc {
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390 newskip <- _toskip map: :inst {
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391 inst assignRegs: assignments withSource: regSrc
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392 }
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393 skipIf: _cond newskip
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394 }
185
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395 }
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396 }
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397
189
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diff changeset
398 allocRegs:withSource <- :instarr:regSrc {
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399 _regMap <- dict linear
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400 _argMap <- dict linear
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401
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402 _usageTracker <- :_firstUsage {
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403 #{
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404 firstUsage <- _firstUsage
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405 lastUsage <- _firstUsage
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406 useCount <- 0
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407 maxSize <- byte
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408 usedAt:withSize <- :address :size {
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diff changeset
409 useCount <- useCount + 1
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diff changeset
410 lastUsage <- address
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diff changeset
411 if: size > maxSize {
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diff changeset
412 maxSize <- size
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diff changeset
413 }
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diff changeset
414 }
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diff changeset
415 string <- {
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diff changeset
416 "Uses: " . useCount . ", FirstUse: " . (firstUsage join: ":") . ", Last Use: " . (lastUsage join: ":") . ", Max Size: " . maxSize
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diff changeset
417 }
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diff changeset
418 }
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diff changeset
419 }
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diff changeset
420
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diff changeset
421 _maxUses <- 0
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diff changeset
422 regUsage <- #{
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diff changeset
423 reg:usedAt:withSize <- :reg :address :size {
193
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diff changeset
424 raddress <- address reverse
189
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diff changeset
425 usage <- _regMap get: reg elseSet: {
193
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diff changeset
426 _usageTracker: raddress
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
427 }
193
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diff changeset
428 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
429 if: (usage useCount) > _maxUses {
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diff changeset
430 _maxUses <- usage useCount
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diff changeset
431 }
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diff changeset
432 }
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diff changeset
433 arg:usedAt:withSize <- :arg :address :size {
193
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diff changeset
434 raddress <- address reverse
189
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diff changeset
435 usage <- _argMap get: arg elseSet: {
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diff changeset
436 _usageTracker: [0 0]
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diff changeset
437 }
193
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diff changeset
438 usage usedAt: raddress withSize: size
189
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diff changeset
439 }
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diff changeset
440 print <- {
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diff changeset
441 foreach: _regMap :reg usage {
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diff changeset
442 print: (string: reg) . " | " . (string: usage) . "\n"
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diff changeset
443 }
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diff changeset
444 foreach: _argMap :arg usage {
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diff changeset
445 print: (string: arg) . " | " . (string: usage) . "\n"
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diff changeset
446 }
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diff changeset
447 }
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diff changeset
448 }
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diff changeset
449 foreach: instarr :idx inst {
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diff changeset
450 inst recordUsage: regUsage at: [idx]
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diff changeset
451 }
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diff changeset
452 print: regUsage
193
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diff changeset
453
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diff changeset
454 addrLessEq <- :left :right {
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diff changeset
455 lesseq <- true
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diff changeset
456 while: { lesseq && (not: (left empty?)) && (not: (right empty?)) } do: {
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diff changeset
457 if: (left value) > (right value) {
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diff changeset
458 lesseq <- false
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diff changeset
459 } else: {
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diff changeset
460 if: (left value) < (right value) {
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diff changeset
461 left <- []
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diff changeset
462 } else: {
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parents: 189
diff changeset
463 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
464 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
465 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
466 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
467 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
468 lesseq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
469 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
470
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
471 addrGreatEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
472 greateq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
473 while: { greateq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
474 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
475 greateq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
476 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
477 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
478 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
479 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
480 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
481 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
482 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
483 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
484 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
485 greateq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
486 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
487
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
488 liveFrom:to <- :regs :from :to {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
489 live <- #[]
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
490 foreach: regs :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
491 if: ((usage lastUsage) addrGreatEq: from) && ((usage firstUsage) addrLessEq: to) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
492 live append: reg
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
493 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
494 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
495 live
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
496 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
497
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
498 _assignments <- dict linear
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
499 curuses <- _maxUses
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
500 while: { curuses > 0 && (_assignments length) < (_regMap length) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
501 foreach: _regMap :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
502 if: (usage useCount) = curuses {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
503 liveArgs <- _argMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
504 foreach: liveArgs :_ arg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
505 regSrc allocArg: (arg num)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
506 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
507
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
508 liveRegs <- _regMap liveFrom: (usage firstUsage) to: (usage lastUsage)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
509 print: (string: reg) . " | Live: " . (liveRegs join: ", ") . ", Live Args: " . (liveArgs join: ", ") . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
510 foreach: liveRegs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
511 if: (_assignments contains?: reg) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
512 regSrc allocSpecific: (_assignments get: reg)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
513 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
514 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
515 _assignments set: reg (regSrc alloc: (usage maxSize))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
516
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
517 regSrc returnAll
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
518 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
519 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
520 curuses <- curuses - 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
521 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
522 print: "\n\nAssignments:\n\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
523 foreach: _assignments :reg assign {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
524 print: (string: reg) . " = " . assign . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
525 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
526
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
527 //TODO: Save callee saved regs
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
528 map: instarr :inst {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
529 inst assignRegs: _assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
530 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
531 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
532
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
533 //used to convert IL to a format suitable for a 2-operand architecture
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
534 //should be run after register allocation (I think....)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
535 to2Op <- :instarr {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
536 instarr fold: #[] with: :newarr inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
537 if: (inst numops) = 3 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
538 if: (inst inb) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
539 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
540 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
541 if: (inst commutative?) && (inst ina) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
542 newarr append: (op2: (inst opcode) in: (inst inb) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
543 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
544 newarr append: (mov: (inst inb) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
545 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
546 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
547 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
548 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
549 if: (inst numops) = 2 && (inst opcode) != _mov {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
550 if: (inst in) != (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
551 newarr append: (mov: (inst in) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
552 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
553 newarr append: (op1: (inst opcode) val: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
554 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
555 newarr append: inst
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
556 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
557 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
558 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
559 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
560
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
561 main <- {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
562 fib <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
563 sub: 2 (arg: 0) (reg: 0) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
564 skipIf: ge #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
565 return: 1 q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
566 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
567 call: "fib" withArgs: #[reg: 0]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
568 mov: retr (reg: 1) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
569 add: 1 (reg: 0) (reg: 2) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
570 call: "fib" withArgs: #[reg: 2]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
571 add: retr (reg: 1) (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
572 return: (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
573 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
574 print: "Original:\n\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
575 foreach: fib :idx inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
576 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
577 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
578 print: "\n\nUsage:\n\n"
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
579 fiba <- allocRegs: fib withSource: (x86 regSource)
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
580 print: "\n\nAFter Assignment:\n\n"
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
581 foreach: fiba :idx inst {
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
582 print: (string: inst) . "\n"
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
583 }
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
584 fib2 <- to2Op: fiba
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
585 print: "\n\n2-Operand:\n\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
586 foreach: fib2 :idx inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
587 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
588 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
589 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
590 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
591 }