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Mostly complete register allocation in il module with a register source in the x86 module
author Mike Pavone <pavone@retrodev.com>
date Mon, 26 Aug 2013 19:53:16 -0700
parents 97f107b9e8d3
children 30bed95cbb18
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1 {
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2 regnames <- #["rax" "rcx" "rdx" "rbx" "rsp" "rbp" "rsi" "rdi" "r8" "r9" "r10" "r11" "r12" "r13" "r14" "r15"]
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3 uppernames <- #["ah" "ch" "dh" "bh"]
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4 ireg <- :regnum {
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5 #{
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6 num <- { regnum }
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7 reg <- { regnum and 7u8}
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8 string <- { regnames get: regnum }
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9 rm <- :tail { reg or 0xC0u8 | tail }
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10 validforSize? <- :size { true }
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11 isInteger? <- { false }
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12 register? <- { true }
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13 label? <- { false }
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14 upper? <- { true }
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15 needsRex? <- { regnum >= 8u8 }
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16 rexBitReg <- {
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17 if: needsRex? {
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18 4u8
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19 } else: {
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20 0u8
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21 }
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22 }
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23 rexBitRM <- {
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24 if: needsRex? {
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25 1u8
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26 } else: {
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27 0u8
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28 }
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29 }
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30 = <- :other {
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31 (not: (other isInteger?)) && (other register?) && (not: (other upper?)) && regnum = (other num)
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32 }
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33 }
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34 }
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35
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36 upper <- :regnum {
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37 #{
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38 num <- { regnum }
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39 reg <- { regnum }
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40 string <- { uppernames get: regnum - 4 }
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41 rm <- :tail { regnum or 0xC0u8 | tail }
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42 validforSize? <- :size {
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43 size = byte
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44 }
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45 isInteger? <- { false }
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46 register? <- { true }
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47 label? <- { false }
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48 upper? <- { true }
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49 needsRex? <- { false }
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50 = <- :other {
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51 (not: (other isInteger?)) && (other register?) && (other upper?) && regnum = (other num)
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52 }
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53 }
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54 }
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55 fakesrc <- #{
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56 needsRex? <- { false }
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57 rexBitReg <- { 0u8 }
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58 rexBitRM <- { 0u8 }
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59 }
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60 size <- :s {
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61 #{
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62 num <- { s }
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63 = <- :other {
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64 s = (other num)
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65 }
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66 > <- :other {
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67 s > (other num)
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68 }
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69 >= <- :other {
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70 s >= (other num)
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71 }
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72 < <- :other {
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73 s < (other num)
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74 }
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75 <= <- :other {
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76 s <= (other num)
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77 }
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78 needsRex? <- { s = 3 }
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79 rexBit <- {
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80 if: needsRex? {
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81 0x08u8
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82 } else: {
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83 0u8
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84 }
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85 }
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86 }
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87 }
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88 byte <- size: 0
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89 word <- size: 1
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90 dword <- size: 2
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91 qword <- size: 3
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92
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93 condition <- :num {
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94 #{
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95 cc <- { num }
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96 }
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97 }
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98 _o <- condition: 0u8
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99 _no <- condition: 1u8
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100 _c <- condition: 2u8
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101 _nc <- condition: 3u8
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102 _z <- condition: 4u8
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103 _nz <- condition: 5u8
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104 _be <- condition: 6u8
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105 _nbe <- condition: 7u8
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106 _s <- condition: 8u8
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107 _ns <- condition: 9u8
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108 _p <- condition: 10u8
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109 _np <- condition: 11u8
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110 _l <- condition: 12u8
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111 _nl <- condition: 13u8
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112 _le <- condition: 14u8
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113 _nle <- condition: 15u8
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114
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115
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116 size_bit <- :opcode size {
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117 if: size = byte {
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118 opcode
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119 } else: {
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120 opcode or 1u8
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121 }
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122 }
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123 opex <- :val {
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124 #{
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125 reg <- { val }
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126 string <- { "opex " . val}
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127 }
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128 }
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129
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130 mod_rm:withTail <- :register regmem :end {
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131 list <- regmem rm: end
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132 (list value) or ( lshift: (register reg) by: 3u8) | (list tail)
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133 }
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134
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135 mod_rm <- :reg rm {
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136 mod_rm: reg rm withTail: []
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137 }
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138
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139 int_op:withTail <- :value size :tail {
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140 if: size >= dword {
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141 tail <- (uint8: (rshift: value by: 16u64)) | (uint8: (rshift: value by: 24u64)) | tail
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142 }
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143 if: size >= word {
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144 tail <- (uint8: (rshift: value by: 8u64)) | tail
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145 }
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146 (uint8: value) | tail
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147 }
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148 int_op <- :value size {
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149 int_op: value size withTail: []
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150 }
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151 //used for mov instructions that support 64-bit immediate operands/offsets
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152 int_op64 <- :value size {
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153 tail <- []
183
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154 value <- uint64: value
175
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155 if: size = qword {
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156 tail <- (uint8: (rshift: value by: 32u64)) | (uint8: (rshift: value by: 40u64)) | (uint8: (rshift: value by: 48u64)) | (uint8: (rshift: value by: 56u64)) | tail
175
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157 }
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158 int_op: value size withTail: tail
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159 }
174
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160
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161 prefix:withInstruction <- :reg rm size :inst {
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162 if: size = word {
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163 inst <- 0x66u8 | inst
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164 }
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165 if: (size needsRex?) || (reg needsRex?) || (rm needsRex?) {
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166 rex <- 0x40u8 or (size rexBit) or (reg rexBitReg) or (rm rexBitRM)
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167 inst <- rex | inst
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168 }
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169 inst
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170 }
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171
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172 _rax <- ireg: 0u8
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173 _rcx <- ireg: 1u8
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174 _rdx <- ireg: 2u8
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175 _rbx <- ireg: 3u8
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176 _rsp <- ireg: 4u8
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177 _rbp <- ireg: 5u8
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178 _rsi <- ireg: 6u8
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179 _rdi <- ireg: 7u8
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180 _r8 <- ireg: 8u8
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181 _r9 <- ireg: 9u8
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182 _r10 <- ireg: 10u8
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183 _r11 <- ireg: 11u8
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184 _r12 <- ireg: 12u8
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185 _r13 <- ireg: 13u8
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186 _r14 <- ireg: 14u8
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187 _r15 <- ireg: 15u8
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188 _ah <- upper: 4u8
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189 _ch <- upper: 5u8
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190 _dh <- upper: 6u8
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191 _bh <- upper: 7u8
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192
193
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193 //AMD64 convention
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194 _argregs <- #[
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195 _rdi
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196 _rsi
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197 _rdx
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198 _rcx
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199 _r8
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200 _r9
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201 ]
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202 _calleesave <- #[
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203 _rbx
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204 _rbp
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205 _r12
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206 _r13
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207 _r14
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208 _r15
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209 ]
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210 _tempregs <- #[
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211 _r10
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212 _r11
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213 _rax
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214 ]
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215
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216
180
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217 inst <- :ilist {
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218 #{
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219 length <- { ilist length }
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220 flattenTo:at <- :dest :idx {
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221 ilist fold: idx with: :idx byte {
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222 dest set: idx byte
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223 idx + 1
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224 }
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225 }
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226 }
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227 }
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228
175
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229 op:withCode:withImmed:withOpEx <- :src dst size :normal :immed :myopex {
174
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230 reg <- src
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231 rm <- dst
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232 base <- if: (src isInteger?) {
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233 reg <- fakesrc
175
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234 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
174
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235 } else: {
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236 if: (src register?) {
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237 (size_bit: normal size) | (mod_rm: src dst)
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238 } else: {
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239 reg <- dst
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240 rm <- src
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241 (size_bit: normal or 0x02u8 size) | (mod_rm: dst src)
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242 }
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243 }
180
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244 inst: (prefix: reg rm size withInstruction: base)
174
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245 }
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246
175
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247 op:withCode:withImmed:withImmedRax:withOpEx:withByteExtend <- :src dst size :normal :immed :immedRax :myopex :byteExt {
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248 reg <- src
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249 rm <- dst
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250 if: (src isInteger?) {
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251 reg <- fakesrc
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252 base <- if: size > byte && (((src signed?) && src < 128 && src >= -128) || ((not: (src signed?)) && src < 256)) {
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253 byteExt | (mod_rm: (opex: myopex) dst withTail: [(uint8: src)])
175
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254 } else: {
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255 if: dst = _rax {
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256 (size_bit: immedRax size) | (int_op: src size)
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257 } else: {
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258 (size_bit: immed size) | (mod_rm: (opex: myopex) dst withTail: (int_op: src size))
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259 }
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260 }
180
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261 inst: (prefix: reg rm size withInstruction: base)
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262 } else: {
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263 op: src dst size withCode: normal withImmed: immed withOpEx: myopex
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264 }
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265 }
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266
183
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267 _jmprel <- :op jmpDest {
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268 }
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269
174
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270 #{
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271 rax <- { _rax }
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272 rcx <- { _rcx }
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273 rdx <- { _rdx }
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274 rbx <- { _rbx }
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275 rsp <- { _rsp }
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276 rbp <- { _rbp }
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277 rsi <- { _rsi }
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278 rdi <- { _rdi }
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279 r8 <- { _r8 }
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280 r9 <- { _r9 }
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281 r10 <- { _r10 }
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282 r11 <- { _r11 }
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283 r12 <- { _r12 }
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284 r13 <- { _r13 }
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285 r14 <- { _r14 }
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286 r15 <- { _r15 }
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287 ah <- { _ah }
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288 ch <- { _ch }
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289 dh <- { _dh }
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290 bh <- { _bh }
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291
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292 b <- { byte }
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293 w <- { word }
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294 d <- { dword }
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295 q <- { qword }
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296
183
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297 o <- { _o }
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298 no <- { _no }
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299 c <- { _c }
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300 nc <- { _nc }
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301 ae <- { _nc }
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302 z <- { _z }
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303 e <- { _z }
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304 nz <- { _nz }
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305 ne <- { _nz }
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306 be <- { _be }
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307 nbe <- { _nbe }
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308 a <- { _nbe }
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309 s <- { _s }
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310 ns <- { _ns }
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311 p <- { _p }
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312 pe <- { _p }
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313 np <- { _np }
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314 po <- { _np }
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315 l <- { _l }
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316 nl <- { _nl }
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317 ge <- { _nl }
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318 le <- { _le }
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319 nle <- { _nle }
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320 g <- { _nle }
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321
174
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322 add <- :src dst size {
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323 op: src dst size withCode: 0u8 withImmed: 0x80u8 withImmedRax: 0x04u8 withOpEx: 0u8 withByteExtend: 0x83u8
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324 }
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325
175
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326 sub <- :src dst size {
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327 op: src dst size withCode: 0x28u8 withImmed: 0x80u8 withImmedRax: 0x2Cu8 withOpEx: 5u8 withByteExtend: 0x83u8
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328 }
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329
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330 mov <- :src dst size {
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331 rm <- dst
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332 if: (src isInteger?) && (dst register?) {
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333 opval <- if: size = byte { 0xB0u8 } else: { 0xB8u8 }
183
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334 base <- opval or (dst reg) | (int_op64: src size)
180
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335 inst: (prefix: fakesrc rm size withInstruction: base)
175
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336 } else: {
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337 op: src dst size withCode: 0x88u8 withImmed: 0xC6u8 withOpEx: 0u8
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338 }
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339 }
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340
180
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341 ret <- { inst: [ 0xC3u8 ] }
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342
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343 label <- {
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344 _offset <- -1
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345 _forwardRefs <- #[]
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346 #{
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347 length <- { 0 }
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348 hasOffset? <- { _offset >= 0 }
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349 offset <- { _offset }
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350 register? <- { false }
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351 label? <- { true }
180
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352 flattenTo:at <- :dest :idx {
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353 if: (not: hasOffset?) {
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354 _offset <- idx
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355 foreach: _forwardRefs :idx fun {
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356 fun: _offset
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357 }
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358 _forwardRefs <- #[]
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359 }
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360 idx
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361 }
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362 withOffset:else <- :fun :elsefun {
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363 if: hasOffset? {
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364 fun: _offset
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365 } else: {
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366 _forwardRefs append: fun
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367 elsefun:
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368 }
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369 }
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370 }
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371 }
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372
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373 jmp <- :jmpDest {
181
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374 if: (jmpDest label?) {
180
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375 _size <- -1
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376 #{
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377 length <- { if: _size < 0 { 5 } else: { _size } }
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378 flattenTo:at <- :dest :idx {
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379 jmpDest withOffset: :off {
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380 if: _size < 0 {
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381 rel <- off - (idx + 2)
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382 if: rel < 128 && rel >= -128 {
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383 _size <- 2
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384 } else: {
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385 rel <- rel - 2
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386 if: rel < 32768 && rel >= -32768 {
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387 _size <- 4
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388 } else: {
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389 _size <- 5
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390 }
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391 }
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392 }
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393 rel <- off - (idx + _size)
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394 if: _size = 2 {
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395 dest set: idx 0xEBu8
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396 dest set: (idx + 1) (uint8: rel)
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397 } else: {
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398 if: _size = 4 {
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399 dest set: idx 0x66u8
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400 dest set: (idx + 1) 0xE9u8
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401 dest set: (idx + 2) (uint8: rel)
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402 dest set: (idx + 3) (uint8: (rshift: rel by: 8))
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403 } else: {
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404 dest set: idx 0xE9u8
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405 dest set: (idx + 1) (uint8: rel)
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406 dest set: (idx + 2) (uint8: (rshift: rel by: 8))
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407 dest set: (idx + 3) (uint8: (rshift: rel by: 16))
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408 dest set: (idx + 4) (uint8: (rshift: rel by: 24))
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409 }
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410 }
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411 } else: {
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412 _size <- 5
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413 }
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414 idx + _size
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415 }
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416 }
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417 } else: {
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diff changeset
418 inst: 0xFFu8 | (mod_rm: (opex: 5u8) jmpDest)
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419 }
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420 }
175
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diff changeset
421
183
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422 jcc <- :cond jmpDest {
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423 _size <- -1
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424 #{
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425 length <- { if: _size < 0 { 5 } else: { _size } }
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diff changeset
426 flattenTo:at <- :dest :idx {
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diff changeset
427 jmpDest withOffset: :off {
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parents: 181
diff changeset
428 if: _size < 0 {
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diff changeset
429 rel <- off - (idx + 2)
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diff changeset
430 if: rel < 128 && rel >= -128 {
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diff changeset
431 _size <- 2
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diff changeset
432 } else: {
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diff changeset
433 _size <- 6
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diff changeset
434 }
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diff changeset
435 }
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diff changeset
436 rel <- off - (idx + _size)
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parents: 181
diff changeset
437 if: _size = 2 {
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diff changeset
438 dest set: idx 0x70u8 or (cond cc)
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diff changeset
439 dest set: (idx + 1) (uint8: rel)
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parents: 181
diff changeset
440 } else: {
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diff changeset
441 dest set: idx 0x0Fu8
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442 dest set: (idx + 1) 0x80u8 or (cond cc)
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diff changeset
443 dest set: (idx + 2) (uint8: rel)
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diff changeset
444 dest set: (idx + 3) (uint8: (rshift: rel by: 8))
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diff changeset
445 dest set: (idx + 4) (uint8: (rshift: rel by: 16))
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diff changeset
446 dest set: (idx + 5) (uint8: (rshift: rel by: 24))
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parents: 181
diff changeset
447 }
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parents: 181
diff changeset
448 } else: {
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449 _size <- 6
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diff changeset
450 }
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diff changeset
451 idx + _size
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diff changeset
452 }
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parents: 181
diff changeset
453 }
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diff changeset
454 }
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parents: 181
diff changeset
455
181
f188723c15b4 Add call instruction to x86 module
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diff changeset
456 call <- :callDest {
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diff changeset
457 if: (callDest label?) {
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diff changeset
458 #{
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459 length <- { 5 }
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diff changeset
460 flattenTo:at <- :dest :idx {
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461 dest set: idx 0xE8u8
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diff changeset
462 callDest withOffset: :off {
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463 rel <- off - (idx + 5)
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464 dest set: (idx + 1) (uint8: rel)
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diff changeset
465 dest set: (idx + 2) (uint8: (rshift: rel by: 8))
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parents: 180
diff changeset
466 dest set: (idx + 3) (uint8: (rshift: rel by: 16))
f188723c15b4 Add call instruction to x86 module
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diff changeset
467 dest set: (idx + 4) (uint8: (rshift: rel by: 24))
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
468 } else: {
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
469 }
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diff changeset
470 idx + 5
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parents: 180
diff changeset
471 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
472 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
473 } else: {
f188723c15b4 Add call instruction to x86 module
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diff changeset
474 inst: 0xFFu8 | (mod_rm: (opex: 2u8) callDest)
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
475 }
f188723c15b4 Add call instruction to x86 module
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parents: 180
diff changeset
476 }
174
8b5829372ad1 Initial work on x86 instruction encoding module
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parents:
diff changeset
477
183
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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diff changeset
478 push <- :src {
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diff changeset
479 if: (src isInteger?) {
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parents: 181
diff changeset
480 if: src < 128 && src > -128 {
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diff changeset
481 inst: 0x6Au8 | (uint8: src)
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parents: 181
diff changeset
482 } else: {
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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diff changeset
483 inst: 0x68u8 | (uint8: src) | (uint8: (rshift: src by: 8)) | (uint8: (rshift: src by: 16)) | (uint8: (rshift: src by: 24))
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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diff changeset
484 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
485 } else: {
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diff changeset
486 base <- if: (src register?) {
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parents: 181
diff changeset
487 [0x50u8 or (src reg)]
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parents: 181
diff changeset
488 } else: {
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diff changeset
489 0xFFu8 | (mod_rm: (opex: 6u8) src)
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diff changeset
490 }
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diff changeset
491 inst: (prefix: fakesrc src d withInstruction: base)
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diff changeset
492 }
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parents: 181
diff changeset
493 }
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diff changeset
494
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diff changeset
495 pop <- :dst {
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diff changeset
496 base <- if: (dst register?) {
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parents: 181
diff changeset
497 [0x58u8 or (dst reg)]
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parents: 181
diff changeset
498 } else: {
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parents: 181
diff changeset
499 0x8Fu8 | (mod_rm: (opex: 0u8) dst)
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diff changeset
500 }
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diff changeset
501 inst: (prefix: fakesrc dst d withInstruction: base)
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parents: 181
diff changeset
502 }
97f107b9e8d3 Fix a few bugs in the x86 module and add jcc, push and pop instructions
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parents: 181
diff changeset
503
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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diff changeset
504 //TODO: support multiple calling conventions
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diff changeset
505 regSource <- {
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diff changeset
506 _used <- 0
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diff changeset
507 _usedAllTime <- 0
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diff changeset
508 _nextStackOff <- 0
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diff changeset
509 _findUnused <- :size reglists{
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diff changeset
510 found <- -1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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diff changeset
511 foundlist <- -1
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parents: 183
diff changeset
512 curlist <- 0
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parents: 183
diff changeset
513 ll <- reglists length
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diff changeset
514 while: { found < 0 && curlist < ll } do: {
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parents: 183
diff changeset
515 cur <- 0
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parents: 183
diff changeset
516 regs <- reglists get: curlist
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parents: 183
diff changeset
517 len <- regs length
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diff changeset
518 while: { found < 0 && cur < len } do: {
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parents: 183
diff changeset
519 bit <- lshift: 1 by: cur
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parents: 183
diff changeset
520 if: (_used and bit) = 0 {
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parents: 183
diff changeset
521 found <- cur
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parents: 183
diff changeset
522 foundlist <- regs
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parents: 183
diff changeset
523 _used <- _used or bit
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parents: 183
diff changeset
524 _usedAllTime <- _usedAllTime or bit
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diff changeset
525 }
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parents: 183
diff changeset
526 cur <- cur + 1
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parents: 183
diff changeset
527 }
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parents: 183
diff changeset
528 curlist <- curlist + 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
529 }
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parents: 183
diff changeset
530 if: found >= 0 {
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diff changeset
531 foundlist get: found
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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diff changeset
532 } else: {
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parents: 183
diff changeset
533 myoff <- _nextStackOff
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diff changeset
534 _nextStackOff <- _nextStackOff + size
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parents: 183
diff changeset
535 il base: _rsp offset: myoff
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parents: 183
diff changeset
536 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
537 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
538 #{
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parents: 183
diff changeset
539 alloc <- :size {
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parents: 183
diff changeset
540 _findUnused: size #[
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parents: 183
diff changeset
541 _calleesave
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parents: 183
diff changeset
542 _tempregs
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parents: 183
diff changeset
543 _argregs
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parents: 183
diff changeset
544 ]
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parents: 183
diff changeset
545 }
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parents: 183
diff changeset
546 //used to allocate a register
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parents: 183
diff changeset
547 //that will be returned before a call
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parents: 183
diff changeset
548 allocTemp <- :size {
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parents: 183
diff changeset
549 _findUnused: size #[
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parents: 183
diff changeset
550 _tempregs
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parents: 183
diff changeset
551 _argregs
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parents: 183
diff changeset
552 _calleesave
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parents: 183
diff changeset
553 ]
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
554 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
555 //allocated the return register
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 183
diff changeset
556 allocRet <- :size {
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parents: 183
diff changeset
557 bit <- (lshift: 1 by: (_rax num))
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parents: 183
diff changeset
558 _used <- _used or bit
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parents: 183
diff changeset
559 _usedAllTime <- _usedAllTime or bit
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560 _rax
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561 }
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562 allocArg <- :argnum {
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563 if: argnum < (_argregs length) {
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564 reg <- _argregs get: argnum
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565 bit <- (lshift: 1 by: (reg num))
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566 _used <- _used or bit
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567 _usedAllTime <- _usedAllTime or bit
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568 } else: {
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569 il base: _rsp offset: _nextStackOff + 8 * (argnum - (_argregs length))
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570 }
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571 }
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572 allocSpecific <- :reg {
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573 if: (reg register?) {
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574 bit <- (lshift: 1 by: (reg num))
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575 _used <- _used or bit
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576 }
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577 }
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578 stackSize <- { _nextStackOff }
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579 return <- :reg {
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580 _used <- _used and (0xF xor (lshift: 1 by: (reg num)))
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581 }
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582 returnAll <- { _used = 0 }
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583 needSaveProlog <- {
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584 retval <- #[]
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585 foreach: _calleesave :idx reg {
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586 if: (_usedAllTime and (lshift: 1 by: (reg num))) != 0 {
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587 retval append: reg
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588 }
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589 }
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590 retval
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591 }
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592 needSaveForCall <- {
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593 retval <- #[]
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594 foreach: #[_tempregs _argregs] :_ regs {
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595 foreach: regs :_ reg {
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596 if: (_used and (lshift: 1 by: (reg num))) != 0 {
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597 retval append: reg
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598 }
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599 }
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600 }
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601 retval
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602 }
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603 }
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604 }
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605
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606 main <- {
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607 fib <- label:
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608 notbase <- label:
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609 prog <- #[
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610 fib
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611 sub: 2 rdi q
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612 jcc: ge notbase
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613 mov: 1 rax q
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614 ret:
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615
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616 notbase
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617 push: rdi
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618 call: fib
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619 pop: rdi
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620 push: rax
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621 add: 1 rdi q
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622 call: fib
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623 pop: rdi
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624 add: rdi rax q
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625 ret:
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626 ]
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627
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628 ba <- bytearray executableFromBytes: prog
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629 res <- ba runWithArg: 30u64
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630 print: (string: res) . "\n"
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631 0
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632 }
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633 }
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634 }