Mercurial > repos > blastem
annotate lc8951.c @ 2065:02a9846668d1 segacd
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
author | Michael Pavone <pavone@retrodev.com> |
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date | Sat, 29 Jan 2022 17:43:37 -0800 |
parents | 07ed42bd7b4c |
children | a61a8a87410c |
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1 #include "lc8951.h" |
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2 #include "backend.h" |
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3 |
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4 enum { |
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5 COMIN, |
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6 IFSTAT, |
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7 DBCL, |
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8 DBCH, |
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9 HEAD0, |
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10 HEAD1, |
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11 HEAD2, |
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12 HEAD3, |
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13 PTL, |
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14 PTH, |
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15 WAL, |
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16 WAH, |
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17 STAT0, |
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18 STAT1, |
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19 STAT2, |
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20 STAT3, |
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21 |
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22 SBOUT = COMIN, |
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23 IFCTRL = IFSTAT, |
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24 DACL = HEAD0, |
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25 DACH = HEAD1, |
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26 DTTRG = HEAD2, |
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27 DTACK = HEAD3, |
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28 WAL_WRITE = PTL, |
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29 WAH_WRITE = PTH, |
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30 CTRL0 = WAL, |
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31 CTRL1 = WAH, |
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32 PTL_WRITE = STAT0, |
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33 PTH_WRITE = STAT1, |
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34 RESET = STAT3 |
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35 }; |
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36 |
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37 //IFCTRL |
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38 #define BIT_CMDIEN 0x80 |
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39 #define BIT_DTEIEN 0x40 |
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40 #define BIT_DECIEN 0x20 |
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41 #define BIT_CMDBK 0x10 |
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42 #define BIT_DTWAI 0x08 |
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43 #define BIT_STWAI 0x04 |
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44 #define BIT_DOUTEN 0x02 |
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45 #define BIT_SOUTEN 0x01 |
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46 |
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47 //IFSTAT |
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48 #define BIT_CMDI 0x80 |
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49 #define BIT_DTEI 0x40 |
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50 #define BIT_DECI 0x20 |
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51 #define BIT_DTBSY 0x08 |
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52 #define BIT_STBSY 0x04 |
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53 #define BIT_DTEN 0x02 |
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54 #define BIT_STEN 0x01 |
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55 |
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56 //CTRL0 |
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57 #define BIT_DECEN 0x80 |
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58 #define BIT_WRRQ 0x04 |
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59 |
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60 //STAT3 |
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61 #define BIT_VALST 0x80 |
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62 |
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63 //datasheet timing info |
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64 //3 cycles for memory operation |
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65 //6 cycles min for DMA-mode host transfer |
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66 |
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67 void lc8951_init(lc8951 *context, lcd8951_byte_recv_fun byte_handler, void *handler_data) |
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68 { |
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69 //This seems to vary somewhat between Sega CD models |
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70 //unclear if the difference is in the lc8951 or gate array |
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71 context->regs[IFSTAT] = 0xFF; |
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72 context->ar_mask = 0x1F; |
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73 context->clock_step = (2 + 2) * 6; // external divider, internal divider + DMA period |
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74 context->byte_handler = byte_handler; |
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75 context->handler_data = handler_data; |
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76 context->decode_end = CYCLE_NEVER; |
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77 context->transfer_end = CYCLE_NEVER; |
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78 } |
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79 |
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80 void lc8951_reg_write(lc8951 *context, uint8_t value) |
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81 { |
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82 printf("CDC write %X: %X\n", context->ar, value); |
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83 switch (context->ar) |
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84 { |
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85 case SBOUT: |
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86 context->regs[context->ar] = value; |
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87 if (context->ifctrl & BIT_SOUTEN) { |
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88 context->regs[IFSTAT] &= ~BIT_STBSY; |
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89 } |
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90 break; |
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91 case IFCTRL: |
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92 context->ifctrl = value; |
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93 if (!(value & BIT_SOUTEN)) { |
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94 context->regs[IFSTAT] |= BIT_STBSY; |
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95 } |
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96 if (!(value & BIT_DOUTEN)) { |
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97 context->regs[IFSTAT] |= BIT_DTBSY; |
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98 context->transfer_end = CYCLE_NEVER; |
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99 } |
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100 break; |
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101 case DBCL: |
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102 context->regs[context->ar] = value; |
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103 break; |
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104 case DBCH: |
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105 context->regs[context->ar] = value & 0xF; |
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106 break; |
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107 case DACL: |
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108 context->dac &= 0xFF00; |
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109 context->dac |= value; |
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110 break; |
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111 case DACH: |
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112 context->dac &= 0xFF; |
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113 context->dac |= value << 8; |
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114 break; |
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115 case DTTRG: |
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116 if (context->ifctrl & BIT_DOUTEN) { |
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117 context->regs[IFSTAT] &= ~BIT_DTBSY; |
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118 uint16_t transfer_size = context->regs[DBCL] | (context->regs[DBCH] << 8); |
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119 context->transfer_end = context->cycle + transfer_size * context->clock_step; |
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120 printf("DTTRG: size %u, cycle %u, end %u\n", transfer_size, context->cycle, context->transfer_end); |
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121 } |
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122 break; |
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123 case DTACK: |
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124 context->regs[IFSTAT] |= BIT_DTEI; |
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125 break; |
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126 case WAL_WRITE: |
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127 context->regs[WAL] = value; |
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128 break; |
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129 case WAH_WRITE: |
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130 context->regs[WAH] = value; |
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131 break; |
2062
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Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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132 case CTRL0: |
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133 context->ctrl0 = value; |
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134 break; |
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Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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135 case CTRL1: |
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136 context->ctrl1 = value; |
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|
137 break; |
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Initial work on CDC emulation
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138 case PTL_WRITE: |
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139 context->regs[PTL] = value; |
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140 break; |
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Initial work on CDC emulation
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141 case PTH_WRITE: |
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142 context->regs[PTH] = value; |
2062
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143 context->ptl_internal = (context->regs[PTL] | (context->regs[PTH] << 8)) & (sizeof(context->buffer) - 1); |
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Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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144 context->decoding = 1; |
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145 context->decode_end = context->cycle + 2352 * context->clock_step * 4; |
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146 break; |
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147 case RESET: |
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148 context->comin_count = 0; |
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149 context->regs[IFSTAT] = 0xFF; |
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150 break; |
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Initial work on CDC emulation
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151 default: |
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152 break; |
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153 } |
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154 if (context->ar != SBOUT) { |
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155 context->ar++; |
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156 context->ar &= context->ar_mask; |
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157 } |
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158 } |
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159 |
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160 uint8_t lc8951_reg_read(lc8951 *context) |
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161 { |
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162 uint8_t value; |
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163 if (context->ar == COMIN) { |
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164 if (!context->comin_count) { |
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165 return 0xFF; |
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166 } |
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167 value = context->comin[(context->comin_write - context->comin_count)&sizeof(context->comin)]; |
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168 context->comin_count--; |
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169 if (!context->comin_count) { |
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170 context->regs[IFSTAT] |= BIT_CMDI; |
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171 } |
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172 return value; |
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|
173 } |
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174 if (context->ar == STAT3) { |
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175 context->regs[IFSTAT] |= BIT_DECI; |
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|
176 } |
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177 if (context->ar >= sizeof(context->regs)) { |
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|
178 value = 0xFF; |
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|
179 } else { |
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|
180 value = context->regs[context->ar]; |
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|
181 } |
2062
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182 printf("CDC read %X: %X\n", context->ar, value); |
2058
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183 context->ar++; |
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184 context->ar &= context->ar_mask; |
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185 return value; |
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|
186 } |
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Initial work on CDC emulation
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187 |
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188 void lc8951_ar_write(lc8951 *context, uint8_t value) |
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189 { |
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190 context->ar = value & context->ar_mask; |
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|
191 } |
2062
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|
192 |
07ed42bd7b4c
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193 //25 MHz clock input (1/2 SCD MCLK) |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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194 //internal /2 divider |
07ed42bd7b4c
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195 //3 cycles for each SRAM access (though might be crystal frequency rather than internal frequency) |
07ed42bd7b4c
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196 //6 cycle period for DMA transfer out |
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Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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197 // |
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198 |
07ed42bd7b4c
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199 void lc8951_run(lc8951 *context, uint32_t cycle) |
07ed42bd7b4c
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diff
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|
200 { |
07ed42bd7b4c
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201 for(; context->cycle < cycle; context->cycle += context->clock_step) |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
202 { |
07ed42bd7b4c
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diff
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|
203 if (context->cycle >= context->decode_end) { |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
204 context->decode_end = CYCLE_NEVER; |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
changeset
|
205 context->regs[IFSTAT] &= ~BIT_DECI; |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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2058
diff
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|
206 context->regs[STAT3] &= ~BIT_VALST; |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
2058
diff
changeset
|
207 uint16_t block_start = (context->regs[PTL] | (context->regs[PTH] << 8)) & (sizeof(context->buffer)-1); |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
208 for (int reg = HEAD0; reg < PTL; reg++) |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
2058
diff
changeset
|
209 { |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
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diff
changeset
|
210 printf("Setting HEAD%d to buffer[%X]\n", reg - HEAD0, block_start); |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
2058
diff
changeset
|
211 context->regs[reg] =context->buffer[block_start++]; |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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2058
diff
changeset
|
212 block_start &= (sizeof(context->buffer)-1); |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
2058
diff
changeset
|
213 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
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diff
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|
214 printf("Decode done %X:%X:%X mode %X\n", context->regs[HEAD0], context->regs[HEAD1], context->regs[HEAD2], context->regs[HEAD3]); |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
2058
diff
changeset
|
215 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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parents:
2058
diff
changeset
|
216 if (context->transfer_end != CYCLE_NEVER) { |
2065
02a9846668d1
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2062
diff
changeset
|
217 if (context->byte_handler(context->handler_data, context->buffer[context->dac & (sizeof(context->buffer)-1)])) { |
02a9846668d1
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diff
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|
218 context->dac++; |
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diff
changeset
|
219 context->regs[DBCL]--; |
02a9846668d1
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|
220 if (context->regs[DBCL] == 0xFF) { |
02a9846668d1
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diff
changeset
|
221 context->regs[DBCH]--; |
02a9846668d1
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|
222 if (context->regs[DBCH] == 0xFF) { |
02a9846668d1
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diff
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|
223 context->regs[IFSTAT] &= ~BIT_DTEI; |
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|
224 context->regs[IFSTAT] |= BIT_DTBSY; |
02a9846668d1
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225 if (context->cycle != context->transfer_end) { |
02a9846668d1
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diff
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|
226 printf("Expected transfer end at %u but ended at %u\n", context->transfer_end, context->cycle); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
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diff
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|
227 } |
02a9846668d1
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diff
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|
228 context->transfer_end = CYCLE_NEVER; |
2062
07ed42bd7b4c
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parents:
2058
diff
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|
229 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
230 } |
2065
02a9846668d1
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diff
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231 } else { |
02a9846668d1
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|
232 // pause transfer |
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|
233 context->transfer_end = CYCLE_NEVER; |
2062
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
234 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
235 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
236 } |
07ed42bd7b4c
Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
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diff
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|
237 } |
07ed42bd7b4c
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|
238 |
2065
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|
239 void lc8951_resume_transfer(lc8951 *context) |
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|
240 { |
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|
241 if (context->transfer_end == CYCLE_NEVER && (context->ifctrl & BIT_DOUTEN)) { |
02a9846668d1
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|
242 uint16_t transfer_size = context->regs[DBCL] | (context->regs[DBCH] << 8); |
02a9846668d1
Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
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parents:
2062
diff
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243 if (transfer_size) { |
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244 context->transfer_end = context->cycle + transfer_size * context->clock_step; |
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245 printf("RESUME: size %u, cycle %u, end %u\n", transfer_size, context->cycle, context->transfer_end); |
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246 } |
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247 } |
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248 } |
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249 |
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250 void lc8951_write_byte(lc8951 *context, uint32_t cycle, int sector_offset, uint8_t byte) |
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251 { |
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252 lc8951_run(context, cycle); |
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253 uint16_t current_write_addr = context->regs[WAL] | (context->regs[WAH] << 8); |
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254 if (sector_offset == 12) { |
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255 //we've recevied the sync pattern for the next block |
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256 |
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257 //header/status regs no longer considered "valid" |
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258 context->regs[STAT3] |= BIT_VALST; |
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259 if ((context->ctrl0 & (BIT_DECEN|BIT_WRRQ)) == (BIT_DECEN|BIT_WRRQ)) { |
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260 uint16_t block_start = current_write_addr - 2352; |
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261 context->regs[PTL] = block_start; |
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262 context->regs[PTH] = block_start >> 8; |
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263 printf("Decoding block starting at %X\n", block_start); |
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264 context->ptl_internal = block_start & (sizeof(context->buffer)-1); |
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265 context->decode_end = context->cycle + 2352 * context->clock_step * 4; |
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266 } |
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267 } |
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268 if (sector_offset >= 12 && sector_offset < 16) { |
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269 //TODO: Handle SHDREN = 1 |
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270 if ((context->ctrl0 & (BIT_DECEN|BIT_WRRQ)) == (BIT_DECEN)) { |
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271 //monitor only mode |
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272 context->regs[HEAD0 + sector_offset - 12] = byte; |
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273 } |
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274 } |
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275 if ((context->ctrl0 & (BIT_DECEN|BIT_WRRQ)) == (BIT_DECEN|BIT_WRRQ)) { |
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276 context->buffer[current_write_addr & (sizeof(context->buffer)-1)] = byte; |
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277 context->regs[WAL]++; |
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278 if (!context->regs[WAL]) { |
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279 context->regs[WAH]++; |
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280 } |
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281 } |
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282 } |
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283 |
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284 uint32_t lc8951_next_interrupt(lc8951 *context) |
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285 { |
2065
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286 if ((~context->regs[IFSTAT]) & context->ifctrl & (BIT_CMDI|BIT_DTEI|BIT_DECI)) { |
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287 //interrupt already pending |
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288 return context->cycle; |
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289 } |
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290 uint32_t deci_cycle = CYCLE_NEVER; |
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291 if (context->ifctrl & BIT_DECI) { |
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292 deci_cycle = context->decode_end; |
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293 } |
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294 uint32_t dtei_cycle = CYCLE_NEVER; |
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295 if (context->ifctrl & BIT_DTEI) { |
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296 dtei_cycle = context->transfer_end; |
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297 } |
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298 return deci_cycle < dtei_cycle ? deci_cycle : dtei_cycle; |
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299 } |